# US 2019/0377702 A1 · I3c single data rate write flow control

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- Number: US 2019/0377702 A1
- Document ID: US20190377702A1
- Status: Published application
- Kind: A1
- Application number: 16/405,637
- Filed: 2019-05-07
- Published: 2019-12-12
- Earliest claimed: 2018-06-07
- Assignees: QUALCOMM Incorporated
- Applicants: QUALCOMM Incorporated
- Inventors: Radu PITIGOI-ARON; Chandan Pramod ATTARDE; Richard Dominic WIETFELDT; Lalan Jee MISHRA
- Web page: https://patentgrep.com/patent/US20190377702A1

## CPC

- G06F 13/4291: {using a clocked protocol}
- G06F 2213/0016: Inter-integrated circuit (I2C)
- G06F 2213/0038: System on Chip
- G06F 2213/0056: Use of address and non-data lines as data lines for specific data transfers to temporarily enlarge the data bus and increase information transfer rate
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Systems, methods, and apparatus for communication over a serial bus in accordance with an I3C protocol are described that enable a slave device to request that a bus master device terminate a write transaction with the slave device. The serial bus may be operated according to an I3C single data rate protocol. In various aspects of the disclosure, a method performed at a master device coupled to a serial bus includes initiating a write transaction between the master device and a slave device, where the write transaction includes a plurality of data frames, and at least one data frame is configured with a transition bit in place of a parity bit. The method may include terminating the write transaction when the slave device drives a data line of the serial bus while receiving the transition bit.

## Claims

### Claim 1

A method performed at a master device coupled to a serial bus, comprising:
initiating a write transaction between the master device and a slave device, wherein the write transaction includes a plurality of data frames, and at least one data frame is configured with a transition bit in place of a parity bit; and
terminating the write transaction when the slave device drives a data line of the serial bus while receiving the transition bit.

### Claim 2 (depends on 1)

The method of claim 1, wherein terminating the write transaction comprises:
transmitting signaling corresponding to a repeated START condition defined by a protocol used to control communications over the serial bus.

### Claim 3 (depends on 2)

The method of claim 2, wherein terminating the write transaction further comprises:
transmitting signaling corresponding to a STOP condition defined by the protocol used to control communications over the serial bus after transmitting the repeated START condition.

### Claim 4 (depends on 1)

The method of claim 1, wherein terminating the write transaction comprises:
transmitting signaling corresponding to a STOP condition defined by a protocol used to control communications over the serial bus.

### Claim 5 (depends on 1)

The method of claim 1, further comprising:
providing the transition bit in the at least one data frame by driving the data line of the serial bus to a high state after data bits of the at least one data frame have been transmitted; and
causing a line driver coupled to the data line to enter a high impedance mode after driving the data line of the serial bus to the high state.

### Claim 6 (depends on 5)

The method of claim 5, wherein the data line is maintained at the high state by a pull-up structure.

### Claim 7 (depends on 5)

The method of claim 5, wherein the high impedance mode comprises an open-drain mode.

### Claim 8 (depends on 5)

The method of claim 5, further comprising:
detecting a low state on the data line in a bit interval reserved for the transition bit; and
terminating the write transaction after detecting the low state on the data line.

### Claim 9 (depends on 1)

The method of claim 1, wherein the serial bus is operated in accordance with an I3C single data rate protocol.

### Claim 10

An apparatus adapted to operate as a master device when coupled to a serial bus, the apparatus comprising:
a bus interface circuit configured to couple the apparatus to the serial bus; and
a processing device configured to:
initiate a write transaction between the apparatus and a slave device, wherein the write transaction includes a plurality of data frames, and at least one data frame is configured with a transition bit in place of a parity bit; and
terminate the write transaction when the slave device drives a data line of the serial bus while receiving the transition bit.

### Claim 11 (depends on 10)

The apparatus of claim 10, wherein the processing device is further configured to:
transmit signaling corresponding to a repeated START condition defined by a protocol used to control communications over the serial bus.

### Claim 12 (depends on 11)

The apparatus of claim 11, wherein the processing device is further configured to:
transmit signaling corresponding to a STOP condition defined by the protocol used to control communications over the serial bus after transmitting the repeated START condition.

### Claim 13 (depends on 10)

The apparatus of claim 10, wherein the processing device is further configured to:
transmit signaling corresponding to a STOP condition defined by a protocol used to control communications over the serial bus.

### Claim 14 (depends on 10)

The apparatus of claim 10, wherein the processing device is further configured to:
provide the transition bit in the at least one data frame by driving the data line of the serial bus to a high state after data bits of the at least one data frame have been transmitted; and
cause a line driver coupled to the data line to enter a high impedance mode after driving the data line of the serial bus to the high state.

### Claim 15 (depends on 14)

The apparatus of claim 14, wherein the processing device is further configured to:
detect a low state on the data line in a bit interval reserved for the transition bit; and
terminate the write transaction after detecting the low state on the data line.

### Claim 16

A method performed at a slave device coupled to a serial bus, comprising:
receiving a configuration command from a master device indicating that data frames transmitted during a write transaction include transition bits in place of parity bits;
receiving a first data frame from the serial bus during the write transaction; and
driving a data line of the serial bus while receiving a first transition bit of the first data frame to assert a flow control request.

### Claim 17 (depends on 16)

The method of claim 16, further comprising:
receiving signaling corresponding to a repeated START condition after asserting the flow control request, the repeated START condition being defined by a protocol used to control communications over the serial bus.

### Claim 18 (depends on 17)

The method of claim 17, further comprising:
receiving signaling corresponding to a STOP condition after receiving the repeated START condition.

### Claim 19 (depends on 16)

The method of claim 16, further comprising:
receiving signaling corresponding to a STOP condition defined by a protocol used to control communications over the serial bus after asserting the flow control request.

### Claim 20 (depends on 16)

The method of claim 16, wherein the first transition bit of the first data frame is provided on the data line after eight data bits of the first data frame have been received.

### Claim 21 (depends on 16)

The method of claim 16, wherein the data line is maintained in a high state by a pull-up structure prior to assertion of the flow control request, further comprising:
driving the data line to a low state to assert the flow control request.

### Claim 22 (depends on 16)

The method of claim 16, wherein the serial bus is operated in accordance with an I3C single data rate protocol.

### Claim 23

An apparatus adapted to operate as a slave device when coupled to a serial bus, the apparatus comprising:
a bus interface circuit configured to couple the apparatus to the serial bus; and
a processing device configured to:
receive a configuration command from a master device indicating that data frames transmitted during a write transaction include transition bits in place of parity bits;
receive a first data frame from the serial bus during the write transaction; and
cause the bus interface circuit to assert a flow control request by driving a data line of the serial bus while a first transition bit of the first data frame is being received.

### Claim 24 (depends on 23)

The apparatus of claim 23, wherein the processing device is further configured to:
receive signaling corresponding to a repeated START condition after asserting the flow control request, the repeated START condition being defined by a protocol used to control communications over the serial bus.

### Claim 25 (depends on 24)

The apparatus of claim 24, wherein the processing device is further configured to:
receive signaling corresponding to a STOP condition after receiving the repeated START condition.

### Claim 26 (depends on 23)

The apparatus of claim 23, wherein the processing device is further configured to:
receive signaling corresponding to a STOP condition defined by a protocol used to control communications over the serial bus after asserting the flow control request.

### Claim 27 (depends on 23)

The apparatus of claim 23, wherein the first transition bit of the first data frame is provided on the data line after eight data bits of the first data frame have been received.

### Claim 28 (depends on 23)

The apparatus of claim 23, wherein the data line is maintained in a high state by a pull-up structure prior to assertion of the flow control request, wherein the processing device is further configured to:
cause the bus interface circuit to drive the data line to a low state to assert the flow control request.

### Claim 29 (depends on 23)

The apparatus of claim 23, wherein the serial bus is operated in accordance with an I3C single data rate protocol.