# US 2019/0377701 A1 · Vector decoding in time-constrained double data rate interface > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0377701 A1 - Document ID: US20190377701A1 - Status: Published application - Kind: A1 - Application number: 16/393,081 - Filed: 2019-04-24 - Published: 2019-12-12 - Earliest claimed: 2018-06-08 - Assignees: QUALCOMM Incorporated - Applicants: QUALCOMM Incorporated - Inventors: Lalan Jee MISHRA; Richard Dominic WIETFELDT; Helena Deirdre O'SHEA - Web page: https://patentgrep.com/patent/US20190377701A1 ## CPC - G06F 13/4291: {using a clocked protocol} - G06F 13/364: using independent requests or grants, e.g. using separated request and grant lines - G06F 2213/0016: Inter-integrated circuit (I2C) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Systems, methods, and apparatus for improving throughput of a serial bus are described. A method performed at a device coupled to a serial bus includes detecting a transition in signaling state of a first wire of the serial bus while a first pair of consecutive bits is being received from the first wire of the serial bus, determining that no transition in signaling state of the first wire occurred while a second pair of consecutive bits is being received from the first wire, defining bit values for the first pair of consecutive bits based on direction of the transition in signaling state detected while the first pair of consecutive bits is being received, and sampling the signaling state of the first wire while the second pair of consecutive bits is being received to obtain a bit value used to represent both bits in the second pair of consecutive bits. ## Claims ### Claim 1 A method of data communication, comprising: detecting a transition in signaling state of a first wire of a serial bus while a first pair of consecutive bits is being received from the first wire; determining that no transition in the signaling state of the first wire occurred while a second pair of consecutive bits is being received from the first wire; defining bit values for the first pair of consecutive bits based on direction of the transition in the signaling state of the first wire detected while the first pair of consecutive bits is being received; and sampling the signaling state of the first wire while the second pair of consecutive bits is being received to obtain a bit value used to represent both bits in the second pair of consecutive bits. ### Claim 2 (depends on 1) The method of claim 1, wherein the transition in the signaling state of the first wire occurs when the first pair of consecutive bits have different bit values. ### Claim 3 (depends on 1) The method of claim 1, wherein the first pair of consecutive bits is received during a first cycle of a clock signal transmitted on a second wire of the serial bus, and wherein the transition in the signaling state of the first wire is detected during a sampling window associated with the first cycle of the clock signal and defined for a single data rate protocol. ### Claim 4 (depends on 3) The method of claim 3, wherein the second pair of consecutive bits is received during a second cycle of the clock signal transmitted on the second wire of the serial bus, and wherein the signaling state of the first wire is sampled during a sampling window associated with the second cycle of the clock signal and defined for the single data rate protocol. ### Claim 5 (depends on 1) The method of claim 1, further comprising: combining the first pair of consecutive bits and the second pair of consecutive bits in a first plurality of bits at a data decoder circuit. ### Claim 6 (depends on 5) The method of claim 5, further comprising: binarily inverting bit values in the first pair of consecutive bits and the second pair of consecutive bits when transmissions on the serial bus are polarity inverted. ### Claim 7 (depends on 5) The method of claim 5, further comprising: using an edge detection signal received by the data decoder circuit to select between bit values for each pair of consecutive bits from bit values obtained by sampling the signaling state of the first wire and bit values defined based on direction of a transition in the signaling state while the second pair of consecutive bits is being received. ### Claim 8 (depends on 5) The method of claim 5, further comprising: decoding a second plurality of bits from an encoded clock signal received from a second wire of the serial bus, wherein the clock signal is encoded using pulse-width modulation or phase encoding; and combining the first plurality of bits with the second plurality of bits to obtain at least two bytes of data, wherein the clock signal provides timing used for decoding the first plurality of bits, and wherein each of the second plurality of bits is encoded in direction of transition of edges in the clock signal. ### Claim 9 (depends on 8) The method of claim 8, wherein combining the first plurality of bits with the second plurality of bits comprises: interleaving the first plurality of bits with the second plurality of bits to obtain a first received data byte and a second received data byte. ### Claim 10 (depends on 8) The method of claim 8, wherein the at least two bytes of data are sequentially received from the serial bus. ### Claim 11 (depends on 8) The method of claim 8, wherein the at least two bytes of data are transmitted independently such that a transmission error affecting a first byte of the at least two bytes of data does not affect a second byte of the at least two bytes of data. ### Claim 12 (depends on 1) The method of claim 1, wherein the serial bus is operated in accordance with an Improved Inter-Integrated Circuit (I3C), a radio frequency front-end or a system power management interface single data rate data protocol. ### Claim 13 (depends on 1) The method of claim 1, wherein the serial bus is operated in accordance with an Improved Inter-Integrated Circuit (I3C), a radio frequency front-end or a system power management interface double data rate data protocol. ### Claim 14 An apparatus for data communication comprising: an interface circuit adapted to couple the apparatus to a serial bus; a transition detector circuit configured to: detect a transition in signaling state of a first wire of the serial bus while a first pair of consecutive bits is being received from the first wire, wherein bit values for the first pair of consecutive bits are defined based on direction of the transition in the signaling state of the first wire; and determine that no transition in the signaling state of the first wire occurred while a second pair of consecutive bits is being received from the first wire; and a state sampling circuit configured to: sample the signaling state of the first wire while the second pair of consecutive bits is being received; and provide a sampled bit value derived from the sampled signaling state to represent a bit value for both bits in the second pair of consecutive bits. ### Claim 15 (depends on 14) The apparatus of claim 14, wherein the first pair of consecutive bits is received during a first cycle of a clock signal transmitted on a second wire of the serial bus, and wherein the transition in the signaling state of the first wire is detected during a sampling window associated with the first cycle of the clock signal and defined for a single data rate protocol, and wherein the second pair of consecutive bits is received during a second cycle of the clock signal transmitted on the second wire of the serial bus, and wherein the signaling state of the first wire is sampled during a sampling window associated with the second cycle of the clock signal and defined for the single data rate protocol. ### Claim 16 (depends on 14) The apparatus of claim 14, further comprising: a data decoder circuit configured to: binarily invert bit values in the first pair of consecutive bits and the second pair of consecutive bits when transmissions on the serial bus are polarity inverted; and combine the first pair of consecutive bits and the second pair of consecutive bits in a first plurality of bits. ### Claim 17 (depends on 16) The apparatus of claim 16, wherein the data decoder circuit is further configured to: decode a second plurality of bits from an encoded clock signal received from a second wire of the serial bus, wherein the clock signal is encoded using pulse-width modulation or phase encoding; and combine the first plurality of bits with the second plurality of bits to obtain at least two bytes of data, wherein the clock signal provides timing used for decoding the first plurality of bits, and wherein each of the second plurality of bits is encoded in direction of transition of edges in the clock signal. ### Claim 18 A method of data communications, comprising: encoding primary data in a data signal to be transmitted over a first wire of a serial bus; and providing a phase-encoded clock signal to be transmitted over a second wire of the serial bus, wherein the phase-encoded clock signal provides a plurality of edges indicating when bits of the primary data are to be sampled from the first wire, and wherein secondary data is encoded in direction of transition of the plurality of edges. ### Claim 19 (depends on 18) The method of claim 18, further comprising: providing an internal clock signal that controls timing of communication over the serial bus; and transmitting the data signal over the first wire of the serial bus such that one bit of data is transmitted for each clock cycle of the internal clock signal. ### Claim 20 (depends on 19) The method of claim 19, further comprising: phase encoding the internal clock signal using the secondary data to generate the phase-encoded clock signal to be transmitted over the second wire of the serial bus. ### Claim 21 (depends on 19) The method of claim 19, wherein each of the plurality of edges occurs at a mid-point of a corresponding clock cycle of the internal clock signal. ### Claim 22 (depends on 18) The method of claim 18, wherein the data signal is transmitted at a single data rate over the first wire of the serial bus. ### Claim 23 (depends on 18) The method of claim 18, wherein the serial bus is operated in accordance with an Improved Inter-Integrated Circuit (I3C), a radio frequency front-end or a system power management interface single data rate data protocol. ### Claim 24 (depends on 18) The method of claim 18, wherein the serial bus is operated in accordance with an Improved Inter-Integrated Circuit (I3C), a radio frequency front-end or a system power management interface double data rate data protocol. ### Claim 25 An apparatus comprising: an interface circuit adapted to couple the apparatus to a serial bus; a first data encoder configured to: encode primary data in a data signal to be transmitted over a first wire of the serial bus; and a second data encoder configured to: provide a phase-encoded clock signal to be transmitted over a second wire of the serial bus, wherein the phase-encoded clock signal provides a plurality of edges indicating when bits of the primary data are to be sampled from the first wire, and wherein secondary data is encoded in direction of transition of the plurality of edges. ### Claim 26 (depends on 25) The apparatus of claim 25, further comprising: a clock generation circuit configured to provide an internal clock signal that controls timing of communication over the serial bus, wherein one bit of data is transmitted for each clock cycle of the internal clock signal when the data signal is transmitted over the first wire of the serial bus. ### Claim 27 (depends on 26) The apparatus of claim 26, wherein the second data encoder is further configured to: phase encode the internal clock signal using the secondary data to generate the phase-encoded clock signal to be transmitted over the second wire of the serial bus. ### Claim 28 (depends on 26) The apparatus of claim 26, wherein each of the plurality of edges occurs at a mid-point of a corresponding clock cycle of the internal clock signal. ### Claim 29 (depends on 25) The apparatus of claim 25, wherein the data signal is transmitted at a single data rate over the first wire of the serial bus. ### Claim 30 (depends on 25) The apparatus of claim 25, wherein the serial bus is operated in accordance with an Improved Inter-Integrated Circuit (I3C) protocol, a radio frequency front-end protocol or a system power management interface protocol.