# US 2019/0377697 A1 · Microcomputer > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0377697 A1 - Document ID: US20190377697A1 - Status: Published application - Kind: A1 - Application number: 16/549,480 - Filed: 2019-08-23 - Published: 2019-12-12 - Earliest claimed: 2017-03-28 - Assignees: Denso Corporation - Applicants: Denso Corporation - Inventors: Tatsuya YAMASHITA; Kenji YAMADA - Web page: https://patentgrep.com/patent/US20190377697A1 ## CPC - G06F 13/38: Information transfer, e.g. on bus (G06F13/14 takes precedence) - G06F 9/5027: {the resource being a machine, e.g. CPUs, Servers, Terminals} - G06F 11/1641: {where the comparison is not performed by the redundant processing components} - G06F 15/78: comprising a single central processing unit - G06F 2213/40: Bus coupling - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A microcomputer including first and second CPUs is provided. The first and second CPUs may execute identical control programs in parallel. The microcomputer may control a write access by the first or second CPU. The microcomputer may compare an output of the first CPU with an output of the second CPU. Data is written to a write target unit. The microcomputer outputs a write response signal to the first and second CPUs when a data write destination of the first and second CPUs is the write target unit. The microcomputer outputs an abnormality determination signal when data output from the first CPU mismatches with data output from the second CPU. The microcomputer writes the data to the write target unit when the data write destination of the first and second CPUs is the write target unit and the abnormality determination signal is not input. ## Claims ### Claim 1 A microcomputer comprising: first and second CPUs configured to execute identical control programs in parallel; a write control unit configured to control a write access by the first or second CPU; a determination unit configured to compare an output of the first CPU with an output of the second CPU; and a write target unit to which data is written by the write control unit, wherein: the write control unit is configured to output a write response signal to the first and second CPUs before a write to the write target unit is finished when a data write destination of the first and second CPUs is the write target unit; the determination unit is configured to output an abnormality determination signal to the write control unit when data output from the first CPU mismatches with data output from the second CPU; and the write control unit is configured to write the data to the write target unit when the data write destination of the first and second CPUs is the write target unit and the abnormality determination signal is not input to the write control unit. ### Claim 2 (depends on 1) The microcomputer according to claim 1, further comprising: a first delay unit disposed in a path between the first CPU and the determination unit and configured to add a delay time; and a second delay unit disposed in a path connecting to the second CPU and configured to add the delay time that causes an input time point of the second CPU to the determination unit to be same as an input time point of the first CPU to the determination unit. ### Claim 3 (depends on 2) The microcomputer according to claim 2, wherein the delay time is two cycles of a system clock. ### Claim 4 (depends on 2) The microcomputer according to claim 2, wherein the first CPU is configured to execute the write access to the write control unit via the first delay unit. ### Claim 5 (depends on 2) The microcomputer according to claim 2, wherein the second CPU is configured to execute the write access to the write control unit. ### Claim 6 (depends on 1) The microcomputer according to claim 1, further comprising a dedicated bus configured to connect the write control unit with the write target unit. ### Claim 7 (depends on 6) The microcomputer according to claim 6, wherein: a plurality of the write target unit are provided; and the write control unit is configured to select one of the plurality of write target units and execute a write via the dedicated bus. ### Claim 8 (depends on 6) The microcomputer according to claim 6, wherein: the first CPU is configured to execute a read access to the write target unit via the dedicated bus. ### Claim 9 (depends on 1) The microcomputer according to claim 1, wherein: the abnormality determination signal is input to the write target unit; and the write target unit includes a function that executes an abnormality handling process when the abnormality determination signal is input to the write target unit. ### Claim 10 (depends on 9) The microcomputer according to claim 9, wherein: the abnormality handling process includes an output of system reset request signal. ### Claim 11 (depends on 9) The microcomputer according to claim 9, wherein: the abnormality handling process includes an output of interrupt request to the first and second CPUs. ### Claim 12 (depends on 9) The microcomputer according to claim 9, wherein: the abnormality handling process includes an output of abnormality occurrence signal to an outside. ### Claim 13 A microcomputer comprising: first and second CPUs configured to execute identical control programs in parallel; a write control circuit configured to control a write access by the first or second CPU; a determination circuit configured to compare an output of the first CPU with an output of the second CPU; and a write target circuit to which data is written by the write control circuit, wherein: the write control circuit outputs a write response signal to the first and second CPUs before a write to the write target circuit is finished when a data write destination of the first and second CPUs is the write target circuit; the determination circuit outputs an abnormality determination signal to the write control circuit when data output from the first CPU mismatches with data output from the second CPU; and the write control circuit writes the data to the write target circuit when the data write destination of the first and second CPUs is the write target circuit and the abnormality determination signal is not input to the write control circuit.