# US 2019/0377685 A1 · Mmio addressing using a translation table > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0377685 A1 - Document ID: US20190377685A1 - Status: Published application - Kind: A1 - Application number: 16/003,862 - Filed: 2018-06-08 - Published: 2019-12-12 - Earliest claimed: 2018-06-08 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Christoph Raisch; Marco Kraemer; Carsten Otte; Jonathan D. Bradbury; David Craddock - Web page: https://patentgrep.com/patent/US20190377685A1 ## CPC - G06F 12/1009: using page tables, e.g. page table structures - G06F 12/1081: for peripheral access to main memory, e.g. direct memory access [DMA] - G06F 12/1441: {for a range} - G06F 13/1668: {Details of memory controller} - G06F 2212/1008: Correctness of operation, e.g. memory ordering - G06F 2212/206: Memory mapped I/O - G06F 2212/657: Virtual address space management - G06F 2213/0026: PCI express - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A method for processing an instruction by a processor operationally connected to one or more buses comprises determining the instruction is to access an address of an address space. The address space maps a memory and comprises a range of MMIO addresses. The method determines the address being accessed is within the range of MMIO addresses and translates, based on determining that the address being accessed is within the range of MMIO addresses, the address being accessed using a translation table to a bus identifier identifying one of the buses and a bus address of a bus address space. The bus address space is assigned to the identified bus. The bus address resulting from the translation is assigned to a device accessible via the identified bus. Based on the instruction a request directed to the device is sent via the identified bus to the bus address resulting from the translation. ## Claims ### Claim 1 A method for processing an instruction by a processor, wherein the processor is operationally connected to one or more buses, wherein the method comprises: determining the instruction is to access an address of an address space, wherein the address space maps a memory, and wherein the address space additionally comprises a range of Memory Mapped Input/Output (MMIO) addresses; determining the address being accessed by the instruction is within the range of MMIO addresses; translating, based on the determination that the address being accessed is within the range of MMIO addresses, the address being accessed to a bus identifier identifying one of the buses and a bus address of a bus address space assigned to the identified bus, using a translation table, wherein the bus address resulting from the translation is assigned to a device accessible via the identified bus; and sending, based on the instruction, a request directed to the device via the identified bus to the bus address resulting from the translation. ### Claim 2 (depends on 1) The method of claim 1, wherein the buses are PCIe (Peripheral Component Interconnect Express) buses, wherein the device is a PCIe device, and wherein the bus address is a PCIe bus address. ### Claim 3 (depends on 1) The method of claim 1, wherein the address space comprising the address accessed by the instruction is an absolute partition address space assigned to a partition, wherein the translation table is assigned to the partition, and wherein the instruction is an instruction issued by the partition. ### Claim 4 (depends on 3) The method of claim 3, further comprising: receiving, by the processor, a partition identifier identifying the partition issuing the instruction. ### Claim 5 (depends on 3) The method of claim 3, wherein the translation table contains translations for each address of the MMIO range, wherein each address of the MMIO range has an assigned access indicator which indicates whether an access to the respective address of the MMIO range is allowed. ### Claim 6 (depends on 3) The method of claim 3, wherein the translation table only contains translations for addresses of the MMIO range the partition is allowed to access. ### Claim 7 (depends on 1) The method of claim 1, further comprising: determining, whether the bus address resulting from the translation lies within the range of the bus address space assigned to the bus identified by the bus identifier resulting from the translation. ### Claim 8 (depends on 7) The method of claim 7, wherein the translation table comprises identifiers identifying an upper limit and a lower limit of the bus address space assigned to the bus identified by the bus identifier resulting from the translation for determining whether the resulting bus address lies within the range defined by the upper and a lower limit. ### Claim 9 (depends on 1) The method of claim 1, wherein the address being accessed by the instruction comprises a first section encoding an identifier for identifying the bus identifier. ### Claim 10 (depends on 9) The method of claim 9, wherein the identifier for identifying the bus identifier comprises an entry identifier identifying an entry in the translation table providing the bus identifier. ### Claim 11 (depends on 9) The method of claim 9, wherein the address comprises a second section encoding the bus address of the bus address space assigned to the device accessible via the bus identified by the first section. ### Claim 12 (depends on 1) The method of claim 1, wherein write combine is enabled for the addresses of the MMIO range using an aggregation buffer for aggregating requests. ### Claim 13 (depends on 12) The method of claim 12, wherein for each combination of bus identifier and bus address, two addresses are provided in the MMIO range, wherein a first one of the two addresses is provided for executing a write through to the respective bus address and a second one of the two addresses is provided for executing a write combine to the respective bus address. ### Claim 14 (depends on 1) The method of claim 1, wherein the bus identifier comprises one or more of the following for identifying the bus: a node number, a chip number, a bus unit number, and a bus number. ### Claim 15 A system for processing an instruction by a processor comprising: one or more processors, wherein the one or more processors are operationally connected to one or more buses; and a memory communicatively coupled to the one or more processors, wherein the memory comprises instructions which, when executed by the one or more processors, cause the one or more processors to perform a method comprising: determining the instruction is to access an address of an address space, wherein the address space maps a memory, and wherein the address space additionally comprises a range of Memory Mapped Input/Output (MMIO) addresses; determining the address being accessed by the instruction is within the range of MMIO addresses; translating, based on the determination that the address being accessed is within the range of MMIO addresses, the address being accessed to a bus identifier identifying one of the buses and a bus address of a bus address space assigned to the identified bus, using a translation table, wherein the bus address resulting from the translation is assigned to a device accessible via the identified bus; and sending, based on the instruction, a request directed to the device via the identified bus to the bus address resulting from the translation. ### Claim 16 (depends on 15) The system of claim 15, wherein write combine is enabled for the addresses of the MMIO range using an aggregation buffer for aggregating requests. ### Claim 17 (depends on 16) The system of claim 16, wherein for each combination of bus identifier and bus address, two addresses are provided in the MMIO range, wherein a first one of the two addresses is provided for executing a write through to the respective bus address and a second one of the two addresses is provided for executing a write combine to the respective bus address. ### Claim 18 A computer program product for processing an instruction by a processor, the computer program product comprising a computer readable storage medium having machine executable program instructions embodied therewith, wherein the computer readable storage medium is not a transitory signal per se, the program instructions executable by a computer to perform a method comprising: determining the instruction is to access an address of an address space, wherein the address space maps a memory, and wherein the address space additionally comprises a range of Memory Mapped Input/Output (MMIO) addresses; determining the address being accessed by the instruction is within the range of MMIO addresses; translating, based on the determination that the address being accessed is within the range of MMIO addresses, the address being accessed to a bus identifier identifying one of the buses and a bus address of a bus address space assigned to the identified bus, using a translation table, wherein the bus address resulting from the translation is assigned to a device accessible via the identified bus; and sending, based on the instruction, a request directed to the device via the identified bus to the bus address resulting from the translation. ### Claim 19 (depends on 18) The computer program product of claim 18, wherein write combine is enabled for the addresses of the MMIO range using an aggregation buffer for aggregating requests. ### Claim 20 (depends on 19) The computer program product of claim 19, wherein for each combination of bus identifier and bus address, two addresses are provided in the MMIO range, wherein a first one of the two addresses is provided for executing a write through to the respective bus address and a second one of the two addresses is provided for executing a write combine to the respective bus address.