# US 2019/0377673 A1 · Updating cache using two bloom filters > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0377673 A1 - Document ID: US20190377673A1 - Status: Published application - Kind: A1 - Application number: 16/550,613 - Filed: 2019-08-26 - Published: 2019-12-12 - Earliest claimed: 2017-07-19 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Michael Bar-Joshua; Bartholomew Blaner; Yiftach Benjamini; Michael Grubman - Web page: https://patentgrep.com/patent/US20190377673A1 ## CPC - G06F 12/0246: {in block erasable memory, e.g. flash memory} - G06F 1/3275: {Power saving in memory, e.g. RAM, cache} - G06F 11/073: {in a memory management context, e.g. virtual memory or cache management (memory management G06F12/00; testing of static memory units G11C29/00)} - G06F 12/0864: using pseudo-associative means, e.g. set-associative or hashing - G06F 12/0871: Allocation or management of cache space - G06F 12/0895: of parts of caches, e.g. directory or tag array - G06F 16/22: Indexing; Data structures therefor; Storage structures - G11C 11/5642: {Sensing or reading circuits; Data output circuits} - G06F 12/0802: Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches - G06F 16/134: {Distributed indices} - G06F 2212/225: Hybrid cache memory, e.g. having both volatile and non-volatile portions - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Updating cache devices includes a processor to detect a first set of hash functions and a first bit array corresponding to elements of a cache. In some examples, the processor detects a first instruction to add a new element to the cache and modify the first bit array based on the new element. Additionally, the processor processes a first invalidation operation and generates a second bit array and a second set of hash functions, while processing additional instructions. The processor deletes the first bit array and the first set of hash functions in response to detecting that the second bit array and the second set of hash functions have each been generated. Some examples process a second invalidation operation with the second set of hash functions and the second bit array. ## Claims ### Claim 1 A system for managing a cache comprising: a processor to: generate a second bit array and a second set of hash functions corresponding to elements of a cache while processing additional instructions with a first bit array and a first set of hash functions that correspond to the elements of the cache, responsive to generating the second bit array and the second set of hash functions, delete the first bit array and the first set of hash functions, and process a second invalidation operation using the second set of hash functions and the second bit array. ### Claim 2 (depends on 1) The system of claim 1, wherein the processor is to delete the second bit array and the second set of hash functions in response to processing the second invalidation operation with the second bit array. ### Claim 3 (depends on 1) The system of claim 1, wherein the first bit array and the second bit array are Bloom filters. ### Claim 4 (depends on 1) The system of claim 1, wherein the processor is to: detect at least one element to remove from the first bit array; and prevent bits from being set based on the at least one element during the generation of the second bit array. ### Claim 5 (depends on 1) The system of claim 1, wherein the processor is to designate the first bit array as an active array for invalidation operations until the second bit array is generated. ### Claim 6 (depends on 5) The system of claim 5, wherein the processor is to switch from designating the first bit array as the active array to the second bit array as the active array. ### Claim 7 A computer program product (CPP) for managing a cache comprising: a computer readable storage medium; and computer code stored on a computer readable storage medium, with the computer code including instructions for causing one or more computer processor(s) to perform operations including the following: generating a second bit array and a second set of hash functions while processing additional instructions with a first bit array and a first set of hash functions, responsive to generating the second bit array and the second set of hash functions, deleting the first bit array and the first set of hash functions, and processing a second invalidation operation using the second set of hash functions and the second bit array. ### Claim 8 (depends on 7) The CPP of claim 7, wherein the computer code further includes instructions for causing the one or more computer processor(s) to perform the following operations: deleting the second bit array and the second set of hash functions in response to processing the second invalidation operation with the second bit array. ### Claim 9 (depends on 7) The CPP of claim 7, wherein the first bit array and the second bit array are Bloom filters. ### Claim 10 (depends on 7) The CPP of claim 7, wherein the computer code further includes instructions for causing the one or more computer processor(s) to perform the following operations: detecting at least one element to remove from the first bit array; and preventing bits from being set based on the at least one element during the generation of the second bit array. ### Claim 11 (depends on 7) The CPP of claim 7, wherein the computer code further includes instructions for causing the one or more computer processor(s) to perform the following operations: designating the first bit array as an active array for invalidation operations until the second bit array is generated. ### Claim 12 (depends on 11) The CPP of claim 11, wherein the computer code further includes instructions for causing the one or more computer processor(s) to perform the following operations: switching from designating the first bit array as the active array to the second bit array as the active array. ### Claim 13 A computer-implemented method (CIM) for managing a cache comprising: generating a second bit array and a second set of hash functions while processing additional instructions with a first bit array and a first set of hash functions; responsive to generating the second bit array and the second set of hash functions, deleting the first bit array and the first set of hash functions; and processing a second invalidation operation using the second set of hash functions and the second bit array. ### Claim 14 (depends on 13) The CIM of claim 13, further comprising: deleting the second bit array and the second set of hash functions in response to processing the second invalidation operation with the second bit array. ### Claim 15 (depends on 13) The CIM of claim 13, wherein the first bit array and the second bit array are Bloom filters. ### Claim 16 (depends on 13) The CIM of claim 13, further comprising: detecting at least one element to remove from the first bit array; and preventing bits from being set based on the at least one element during the generation of the second bit array. ### Claim 17 (depends on 13) The CIM of claim 13, further comprising: designating the first bit array as an active array for invalidation operations until the second bit array is generated. ### Claim 18 (depends on 17) The CIM of claim 17, further comprising: switching from designating the first bit array as the active array to the second bit array as the active array.