# US 2019/0377671 A1 · Memory controller with memory resource memory management > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0377671 A1 - Document ID: US20190377671A1 - Status: Published application - Kind: A1 - Application number: 16/551,186 - Filed: 2019-08-26 - Published: 2019-12-12 - Earliest claimed: 2017-05-17 - Assignees: Hewlett Packard Enterprise Development LP - Applicants: Hewlett Packard Enterprise Development LP - Inventors: Mitchel E. Wright; Michael R. Krause; Melvin K. Benedict; Dwight L. Barron - Web page: https://patentgrep.com/patent/US20190377671A1 ## CPC - G06F 12/023: {Free address space management} - G06F 11/20: using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements - G06F 12/0292: {using tables or multilevel address translation means (G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10)} - G06F 13/28: using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) - G06T 11/60: Creating or editing images; Combining images with text - G11C 16/10: Programming or data input circuits - G06F 12/0284: {Multiple user address space allocation, e.g. using different base addresses (interprocessor communication G06F15/163)} - G06F 12/10: Address translation - G06F 12/1027: using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] - G06F 12/1036: for multiple virtual address spaces, e.g. segmentation (G06F12/1045 takes precedence) - G06F 12/109: for multiple virtual address spaces, e.g. segmentation (G06F12/1036 takes precedence) - G06F 2212/1041: Resource optimization - G06F 2212/68: Details of translation look-aside buffer [TLB] - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract In an example implementation according to aspects of the present disclosure, a memory controller is disclosed. The memory controller is communicatively coupleable to a memory resource having a plurality of memory resource regions, which may be associated with a plurality of computing resources. The memory controller may include a memory resource interface to communicatively couple the memory controller to the memory resource and a computing resource interface to communicatively couple the memory controller to the plurality of computing resources. The memory controller may further include a memory resource memory management unit to manage the memory resource. ## Claims ### Claim 1 A memory controller communicatively coupleable to a memory resource having a plurality of memory resource regions being associated with a plurality of computing resources, the memory controller comprising: a memory resource interface to communicatively couple the memory controller to the memory resource; a computing resource interface to communicatively couple the memory controller to the plurality of computing resources; and a memory resource memory management unit to manage the memory resource. ### Claim 2 (depends on 1) The memory controller of claim 1, wherein the memory resource memory management unit further comprises: a transaction module to manage transactions between the memory resource and the plurality of computing resources; and a packet routing module to route packets between an appropriate one of the plurality of computing resources and a respective one of the plurality of memory resource regions associated with the appropriate one of the plurality of computing resources. ### Claim 3 (depends on 1) The memory controller of claim 1, wherein memory resource regions not associated with a particular computing resource are inaccessible to the other computing resources. ### Claim 4 (depends on 1) The memory controller of claim 1, wherein the computing resource is selected from the group consisting of at least one of a system on a chip, a field-programmable gate array, a digital signal processing unit, and a graphic processing unit. ### Claim 5 (depends on 1) The memory controller of claim 1, wherein the memory resource memory management unit performs a memory address translation between a native memory address location of the computing resource and a physical memory address location of the memory resource. ### Claim 6 (depends on 1) The memory controller of claim 1, wherein at least one of the plurality of computing resources further comprises: a native memory management unit to manage a native memory on the computing resource. ### Claim 7 (depends on 6) The memory controller of claim 6, wherein the at least one of the plurality of computing resources further comprises: a processing resource to execute instructions on the computing resource and to read data from and write data to the memory resource region of the memory resource associated with the computing resource via at least one of the plurality of memory controllers. ### Claim 8 A computing system comprising: a memory resource further comprising a plurality of memory resource regions; a plurality of computing resources, each of the plurality of computing resources being associated with one of the plurality of memory resource regions of the memory resource; and a plurality of memory controllers, each memory controller further comprising: a memory resource interface to communicatively couple the memory controller to the memory resource, a computing resource interface to communicatively couple the memory controller to the plurality of computing resources, and a memory resource memory management unit to manage the memory resource region of the memory resource associated with each of the plurality of computing resources. ### Claim 9 (depends on 8) The computing system of claim 8, wherein at least one of the plurality of computing resources further comprises: a native memory management unit to manage a native memory on the computing resource; and a processing resource to execute instructions on the computing resource and to read data from and write data to the memory resource region of the memory resource associated with the computing resource via at least one of the plurality of memory controllers. ### Claim 10 (depends on 8) The computing system of claim 8, wherein the memory resource memory management unit performs a memory address translation between a native memory address location of the computing resource and a physical memory address location of the memory resource. ### Claim 11 (depends on 8) The computing system of claim 8, wherein the plurality of memory controllers and the plurality of computing resources are communicatively coupleable in a mesh configuration. ### Claim 12 (depends on 8) The computing system of claim 8, wherein memory resource regions not associated with a particular computing resource are inaccessible to the other computing resources. ### Claim 13 A method comprising: receiving, through a computing resource interface of a memory controller, at least one of a data read request to read data from a memory resource communicatively coupleable to the memory controller and a data write request to write data to the memory resource; translating, by a memory resource memory management unit of the memory controller, the at least one of the data read request and the data write request between a native memory address location of the computing resource and a physical memory address location of the memory resource; and performing, by the computing resource, the at least one of the data read request and the data write request. ### Claim 14 (depends on 13) The method of claim 13, wherein the physical memory address location is located in a region of the memory resource associated with the computing resource. ### Claim 15 (depends on 13) The method of claim 13, wherein the native memory address location is at least one of a native physical address location and a native virtual memory address location.