# US 2019/0377650 A1 · Systems and methods to prevent system crashes due to link failure in memory mirroring mode

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- Number: US 2019/0377650 A1
- Document ID: US20190377650A1
- Status: Published application
- Kind: A1
- Application number: 16/004,996
- Filed: 2018-06-11
- Published: 2019-12-12
- Earliest claimed: 2018-06-11
- Assignees: Dell Products L.P.
- Applicants: Dell Products L.P.
- Inventors: Tuyet-Huong Thi Nguyen; David Keith Chalfant
- Web page: https://patentgrep.com/patent/US20190377650A1

## CPC

- G06F 11/2069: {Management of state, configuration or failover}
- G06F 3/0619: {in relation to data integrity, e.g. data losses, bit errors}
- G06F 3/065: {Replication mechanisms}
- G06F 3/0673: {Single storage device}
- G06F 3/0683: {Plurality of storage devices}
- G06F 11/1666: {where the redundant component is memory or memory area}
- G06F 11/2087: {with a common controller}
- G06F 13/1668: {Details of memory controller}
- G06F 13/24: using interrupt (G06F13/32 takes precedence)
- G06F 2201/805: Real-time
- G06F 2201/82: Solving problems relating to consistency
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Systems and methods for preventing system crashes due to memory link failure in memory mirroring mode in an information handling system (IHS). The IHS may include a first memory device, a second memory device, and an integrated memory controller (IMC). The IMC may issue write transactions to both the first and second memory devices and issue read transactions to the first memory device when the IMC is in memory mirroring mode. The IMC may transmit a system management interrupt (SMI) with an IMC error to a basic input/output system (BIOS) when a persistent uncorrected IMC error is detected within the first memory device. The BIOS may perform a memory mirror failover process that may cause the IMC to issue the write transactions and the read transactions to the second memory device when the IMC error is a fatal memory link error.

## Claims

### Claim 1

An information handling system (IHS), comprising:
a first memory device;
a second memory device; and
a processor including an integrated memory controller (IMC), the IMC configured to:
issue write transactions to both the first memory device and the second memory device when the IMC is in memory mirroring mode;
issue read transactions to the first memory device when the IMC is in memory mirroring mode; and
transmit a system management interrupt (SMI) with an IMC error to a basic input/output system (BIOS) when a persistent uncorrected IMC error is detected within the first memory device, the processor configured to execute the BIOS to:
receive the SMI with the IMC error from the IMC; and
perform a memory mirror failover process to cause the IMC to issue the write transactions and the read transactions to the second memory device when the IMC error is a fatal memory link error and the IMC is in memory mirroring mode.

### Claim 2 (depends on 1)

The information handling system of claim 1, wherein the BIOS further to:
when the IMC error is a fatal memory link error and the IMC is in memory mirroring mode, transmit a system control interrupt (SCI) with a memory mirror redundancy lost event to an operating system (OS) of the IHS.

### Claim 3 (depends on 1)

The information handling system of claim 1, wherein the BIOS further to:
when the IMC error is a fatal memory link error and the IMC is not in memory mirroring mode, transmit a machine check error (MCE) interrupt with an uncorrectable error to an OS of the IHS.

### Claim 4 (depends on 1)

The information handling system of claim 1, wherein the memory mirror failover process to further cause the IMC to quiesce any outstanding write and read transactions to the first memory device.

### Claim 5 (depends on 1)

The information handling system of claim 1, wherein the first memory device and the second memory device comprise dual in-line memory modules (DIMMs).

### Claim 6 (depends on 1)

The information handling system of claim 1, wherein the information handling system further comprises:
a first memory channel coupled between the IMC and the first memory device; and
a second memory channel coupled between the IMC and the second memory device.

### Claim 7 (depends on 1)

The information handling system of claim 1, wherein the information handling system further comprises:
a first memory channel coupled between the IMC and the first memory device; and
a second memory channel coupled between the IMC and the second memory device, wherein
the IMC communicates with the first memory channel via a first double data rate/double data rate transactional (DDR/DDRT) link, and wherein
the IMC communicates with the second memory channel via a second DDR/DDRT link.

### Claim 8 (depends on 2)

The information handling system of claim 2, wherein the memory mirror redundancy lost event comprises information that describes which DIMM of the first memory device is associated with the fatal memory link error and is to be replaced.

### Claim 9 (depends on 1)

The information handling system of claim 1, wherein the fatal memory link error comprises one of a persistent uncorrectable command error or a persistent uncorrectable address error.

### Claim 10

A method, comprising:
issuing, by an integrated memory controller (IMC), write transactions to both a first memory device and a second memory device of the IHS when the IMC is in memory mirroring mode;
issuing, by the IMC, read transactions to the first memory device when the IMC is in memory mirroring mode;
transmitting, by the IMC, a system management interrupt (SMI) with an IMC error to a basic input/output system (BIOS) of the IHS when a persistent uncorrected IMC error is detected within the first memory device;
receiving, by the BIOS, the SMI with the IMC error from the IMC; and
performing, by the BIOS, a memory mirror failover process to cause the IMC to issue the write transactions and the read transactions to the second memory device when the IMC error is a fatal memory link error and the IMC is in memory mirroring mode.

### Claim 11 (depends on 1)

The method of claim 1, wherein the method further comprises:
when the IMC error is a fatal memory link error and the IMC is in memory mirroring mode, transmitting, by the BIOS, a system control interrupt (SCI) with a memory mirror redundancy lost event to an operating system (OS) of the IHS.

### Claim 12 (depends on 1)

The method of claim 1, wherein the method further comprises:
when the IMC error is a fatal memory link error and the IMC is not in memory mirroring mode, transmitting, by the BIOS, a machine check error (MCE) interrupt with an uncorrectable error to an OS of the IHS.

### Claim 13 (depends on 1)

The method of claim 1, wherein the memory mirror failover process to further cause the IMC to quiesce any outstanding write and read transactions to the first memory device.

### Claim 14 (depends on 1)

The method of claim 1, wherein the first memory device and the second memory device comprise dual in-line memory modules (DIMMs).

### Claim 15 (depends on 1)

The method of claim 1, wherein the information handling system further comprises:
a first memory channel coupled between the IMC and the first memory device; and
a second memory channel coupled between the IMC and the second memory device.

### Claim 16 (depends on 1)

The method of claim 1, wherein the information handling system further comprises:
a first memory channel coupled between the IMC and the first memory device; and
a second memory channel coupled between the IMC and the second memory device, wherein
the IMC communicates with the first memory channel via a first double data rate/double data rate transactional (DDR/DDRT) link, and wherein
the IMC communicates with the second memory channel via a second DDR/DDRT link.

### Claim 17 (depends on 2)

The method of claim 2, wherein the memory mirror redundancy lost event comprises information that describes which DIMM of the first memory device is associated with the fatal memory link error and is to be replaced.

### Claim 18 (depends on 1)

The method of claim 1, wherein the fatal memory link error comprises one of a persistent uncorrectable command error or a persistent uncorrectable address error.