# US 2019/0377634 A1 · Memory controller and memory system including the same

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- Number: US 2019/0377634 A1
- Document ID: US20190377634A1
- Status: Published application
- Kind: A1
- Application number: 16/227,876
- Filed: 2018-12-20
- Published: 2019-12-12
- Earliest claimed: 2018-06-12
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Yong Il JUNG
- Web page: https://patentgrep.com/patent/US20190377634A1

## CPC

- G06F 11/1068: {in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence)}
- G06F 11/1012: {using codes or arrangements adapted for a specific type of error (G06F11/1048 takes precedence)}
- G11C 29/52: Protection of memory contents; Detection of errors in memory contents
- H03M 13/45: Soft decoding, i.e. using symbol reliability information (H03M13/41 takes precedence)
- G11C 2029/0411: {Online error correction}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

There are provided a memory controller and a memory system including the same. The memory controller includes: a processor for generating a command and an address in response to a request from a host, and generating a bin label and a Log Likelihood Ratio (LLR), based on data received from memory devices; a buffer memory for temporarily storing the data, the bin label, and the LLR; and an error correction circuit for performing error correction decoding on the data, using the LLR.

## Claims

### Claim 1

A memory controller comprising:
a processor configured to generate a command and an address in response to a request from a host, and generate a bin label and a Log Likelihood Ratio (LLR), based on data received from memory devices;
a buffer memory configured to temporarily store the data, the bin label, and the LLR; and
an error correction circuit configured to perform error correction decoding on the data using the LLR,
wherein the processor:
when a result of error correction decoding on data read in a first memory device among the memory devices is determined to have failed, temporarily stores a first bin label of the first memory device in at least one page buffer of the first memory device and then performs error correction decoding for a second memory device;
when a result of error correction decoding on data read in the second memory device among the memory devices is determined to have failed, temporarily stores a second bin label used in the error correction decoding of the second memory device in at least one page buffer of the second memory device; and
receives the first bin label temporarily stored in the first memory device to perform error correction decoding on data read in the first memory device using another read voltage.

### Claim 2 (depends on 1)

The memory controller of claim 1, wherein the processor includes:
a command generator configured to generate the command;
a bin label generator configured to generate the bin label based on data received from a selected memory device among the memory devices; and
an LLR generator configured to generate the LLR based on the bin label.

### Claim 3 (depends on 2)

The memory controller of claim 2, wherein the bin label generator generates, as the bin label, a value obtained from all code words of the data received from the selected memory device.

### Claim 4 (depends on 1)

The memory controller of claim 1, wherein the buffer memory includes:
a data storage configured to temporarily store data received from a selected memory device among the memory devices;
a bin label storage configured to temporarily store the bin label; and
an LLR storage configured to temporarily store the LLR.

### Claim 5 (depends on 1)

The memory controller of claim 1, wherein, when the first bin label of the first memory device is temporarily stored in the at least one page buffer of the first memory device, the first bin label temporarily stored in the buffer memory is deleted.

### Claim 6 (depends on 1)

The memory controller of claim 1, wherein the error correction circuit:
when it is determined that an error of the data received from the first or second memory device cannot be corrected, the result of the error correction decoding is output as fail; and
when it is determined that an error of the data received from the first or second memory device can be corrected, the result of the error correction decoding is output as pass.

### Claim 7 (depends on 1)

The memory controller of claim 1,
wherein the first bin label is deleted when the result of the error correction decoding on the data read in the first memory device is determined as pass, and
wherein the second bin label is deleted when the result of the error correction decoding on the data read in the second memory device is determined as pass.

### Claim 8 (depends on 1)

The memory controller of claim 1, wherein, when a sensing operation is performed in the first memory device, the processor receives data from the second memory device and controls the error correction circuit to perform error correction decoding on the data received from the second memory device.

### Claim 9

A memory system comprising:
a first memory device and a second memory device, each of which is configured to store data; and
a memory controller configured to control a read operation of each of the first and second memory devices,
wherein the memory controller:
generates a bin label and an LLR based on first data received from the first memory device;
performs error correction decoding on the first data using the LLR;
when the error correction decoding fails, transmits the bin label to the first memory device; and
receives second data from the second memory device, and performs error correction decoding on the second data.

### Claim 10 (depends on 9)

The memory system of claim 9, wherein each of the first and second memory devices includes:
memory cells configured to store data; and
page buffers configured to sense data of the memory cells through bit lines.

### Claim 11 (depends on 10)

The memory system of claim 10, wherein each of the page buffers includes:
a first latch configured to temporarily store data read from the memory cells; and
a second latch configured to temporarily store the bin label.

### Claim 12 (depends on 11)

The memory system of claim 11, wherein the bin label temporarily stored in the second latch is again output to the memory controller in response to a request from the memory controller.

### Claim 13 (depends on 9)

The memory system of claim 9, wherein the memory controller includes:
to a processor configured to control a select one of the first and second memory devices in response to a request from a host, and generate the bin label and the LLR based on a select one of the first data or the second data, the select data corresponding to the select memory device;
a buffer memory configured to temporarily store the select data, the bin label, and the LLR; and
an error correction circuit configured to perform error correction decoding on the select data based on the LLR.

### Claim 14 (depends on 13)

The memory system of claim 13, wherein the processor includes:
a command generator configured to generate a command for controlling the select memory device in response to the request from the host;
a bin label generator configured to generate the bin label based on data sensed in the select memory device; and
an LLR generator configured to generate the LLR based on the data sensed in the select memory device.

### Claim 15 (depends on 14)

The memory system of claim 14, wherein the bin label generator generates, as the bin label, a value obtained from all code words of the select data.

### Claim 16 (depends on 13)

The memory system of claim 13, wherein the buffer memory includes:
a data storage configured to temporarily store the first or second data;
a bin label storage configured to temporarily store the bin label; and
an LLR storage configured to temporarily store the LLR.

### Claim 17 (depends on 13)

The memory system of claim 13, wherein, when the bin label of the select memory device is temporarily stored in the select memory device, the bin label temporarily stored in the buffer memory is deleted.

### Claim 18 (depends on 13)

The memory system of claim 13, wherein the processor ends the read operation of the memory device, among the first and second memory devices, for which error correction decoding has passed.

### Claim 19

A memory system comprising:
first and second memory devices, each including a memory cell array and at least one page buffer; and
a controller configured to:
control each the first and second memory devices to repeat an operation of sensing data from the corresponding memory cell arrays and outputting the sensed data to the at least one page buffer, using a different read voltage for each sensing operation, until an error-correction operation is successful;
generate a bin label based on the sensed data;
repeat the error-correction operation to the sensed data until the error-correction operation is successful;
control, during the repeated error-correction operations, each of the first and second memory devices to update the bin label in the at least one page buffer at each failure of the error-correction operation for use at each subsequent error-correction operation,
wherein the first and second memory devices share a channel and alternately communicate with the controller through the channel.