# US 2019/0377632 A1 · Method of equalizing bit error rates of memory device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0377632 A1 - Document ID: US20190377632A1 - Status: Published application - Kind: A1 - Application number: 16/358,884 - Filed: 2019-03-20 - Published: 2019-12-12 - Earliest claimed: 2018-06-07 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Eun-chu Oh; Moo-sung Kim; Young-sik Kim; Yong-jun Lee; Jeong-ho Lee - Web page: https://patentgrep.com/patent/US20190377632A1 ## CPC - G06F 11/1044: {with specific ECC/EDC distribution} - G06F 11/076: {by exceeding a count or rate limit, e.g. word- or bit count limit} - G06F 11/1048: {using arrangements adapted for a specific error detection or correction feature} - G06F 11/1068: {in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence)} - G11C 13/0004: {comprising amorphous/crystalline phase transition cells} - G11C 13/0023: {Address circuits or decoders} - G11C 13/0035: {Evaluating degradation, retention or wearout, e.g. by counting writing cycles} - G11C 13/0069: {Writing or programming circuits or methods} - G11C 29/52: Protection of memory contents; Detection of errors in memory contents - G11C 8/06: Address interface arrangements, e.g. address buffers - G11C 11/1653: {Address circuits or decoders} - G11C 11/1675: {Writing or programming circuits or methods} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Provided is a bit error rate equalizing method of a memory device. The memory device selectively performs an error correction code (ECC) interleaving operation according to resistance distribution characteristics of memory cells, when writing a codeword including information data and a parity bit of the information data to a memory cell array. In the ECC interleaving operation according to one example, an ECC sector including information data is divided into a first ECC sub-sector and a second ECC sub-sector, the first ECC sub-sector is written to memory cells of a first memory area having a high bit error rate (BER), and the second ECC sub-sector is written to memory cells of a second memory area having a low BER. ## Claims ### Claim 1 A resistive type memory device comprising: a plurality of banks, each bank comprising a bank row decoder connected to a plurality of word lines of the bank, a bank column decoder connected to a plurality of bit lines of the bank, and a memory cell bank array having memory cells arranged in a plurality of rows and columns, each row of memory cells connected to a corresponding one of the word lines and each column of memory cells being connected to a corresponding one of the bit lines, the memory cells of each bank being organized in a plurality of tiles, each of the memory cells comprising a variable resistor that is programmable to store at least one bit of data; an address register configured to provide sequence of memory addresses, each memory address including a bank address identifying one of the plurality of banks, a row address identifying a word line location within the bank identified by the bank address and a column address identifying a subset of bit lines connected to the word line identified by the row address; a control circuit configured to provide each row address and column address of each memory address stored by the address register respectively to the bank row decoder and column decoder of the bank identified by the bank address of the corresponding memory address; wherein, for at least each memory address of a subset of the memory addresses, the control circuit is configured to modify at least one of the corresponding row address and the corresponding column address such that at least one of the following is true: a relative location of a first word line identified by a first row address within a first bank of the plurality of banks is different from a relative location of a second word line identified by the first row address within a second bank of the plurality of banks, and relative locations of first bit lines identified by a first column address within a first bank of the plurality of banks is different from corresponding relative locations of second bit lines identified by the first column address within a second bank of the plurality of banks. ### Claim 2 (depends on 1) The resistive type memory device of claim 1, wherein, for the subset of the memory addresses, the control circuit is configured to modify the corresponding row address so that the relative location of the first word line identified by the first row address within the first bank of the plurality of banks is different from the relative location of the second word line identified by the first row address within the second bank of the plurality of banks. ### Claim 3 (depends on 2) The resistive type memory device of claim 2, wherein the first word line is located in a first area of the first bank and the second word line is located in a second area of the second bank, wherein the first area comprises memory cells having a higher resistance distribution degradation than memory cells of the second area. ### Claim 4 (depends on 3) The resistive type memory device of claim 3, wherein the first area is located at an edge of the first bank and the second area is located at a center of the second bank. ### Claim 5 (depends on 3) The resistive type memory device of claim 3, wherein the first area is located at an edge of a horizontal block of memory tiles of the first bank through which the first word line extends and the second area is centrally located in a horizontal block of memory tiles of the second bank through which the second word line extends. ### Claim 6 (depends on 2) The resistive type memory device of claim 2, wherein, with respect to the first bank, a sequence of row addresses in numerical order from the lowest row address of the sequence to the highest row address of the sequence sequentially identifies word lines from a first edge of the first bank to a second edge of the first bank, and wherein, with respect to the second bank, the sequence of row addresses in numerical order from the lowest row address of the range to the highest row address of the range sequentially identifies word lines in locational order from a center of the second bank to a first edge of the second bank and then from a second edge of the first bank to a center of the second bank. ### Claim 7 (depends on 2) The resistive type memory device of claim 2, wherein, with respect to the first bank, a sequence of row addresses in numerical order of a range of row addresses from the lowest row address of the range to the highest row address of the range sequentially identifies word lines in locational order arranged from a first edge of a first tile of the first bank to a second edge of the first tile of the first bank, and wherein, with respect to the second bank, the sequence of row addresses in numerical order of the range from the lowest row address of the range to the highest row address of the range sequentially identifies word lines in locational order from a center of a first tile of the second bank to a first edge of the first tile of the second bank and then from a second edge of the first tile of the second bank to a center of the first tile of the second bank. ### Claim 8 (depends on 2) The resistive type memory device of claim 2, wherein the control circuit comprises an address modification circuit configured to invert at least one of the more significant bits of all of the row addresses of the subset of the memory addresses. ### Claim at position 9 9-31. (canceled) ### Claim 32 A resistive type memory device comprising: a plurality of banks, each bank comprising a bank row decoder connected to a plurality of word lines of the bank, a bank column decoder connected to a plurality of bit lines of the bank, and a memory cell bank array having memory cells arranged in a plurality of rows and columns, each row of memory cells connected to a corresponding one of the word lines and each column of memory cells being connected to a corresponding one of the bit lines, the memory cells of each bank being organized in a plurality of tiles, each of the memory cells comprising a variable resistor that is programmable to store at least one bit of data; an address register configured to provide sequence of memory addresses, each memory address including a bank address identifying one of the plurality of banks, a row address identifying a word line location within the bank identified by the bank address and a column address identifying a subset of bit lines connected to the word line identified by the row address; a control circuit configured to provide each row address and column address of each memory address stored by the address register respectively to the bank row decoder and column decoder of the bank identified by the bank address of the corresponding memory address, wherein, for at least each memory address of a subset of the memory addresses, the control circuit is configured to modify at least one of the corresponding row address and the corresponding column address such that at least one of the following is true: wherein a relative location of a first word line identified by a first row address within a first bank of the plurality of banks is different from a relative location of a second word line identified by the first row address within a second bank of the plurality of banks, wherein relative locations of first bit lines identified by a first column address within a first bank of the plurality of banks is different from corresponding relative locations of second bit lines identified by the first column address within a second bank of the plurality of banks, and wherein, for the subset of the memory addresses, the control circuit is configured to modify the corresponding column address so that relative locations of the first bit lines identified by the first column address within the first bank of the plurality of banks are different from corresponding relative locations of second bit lines identified by the first column address within the second bank of the plurality of banks. ### Claim 33 (depends on 32) The resistive type memory device of claim 32, wherein memory cells connected to the first bit lines have a higher resistance distribution degradation than memory cells connected to the second bit lines. ### Claim 34 (depends on 33) The resistive type memory device of claim 33, wherein the first bit lines are located at an edge of the first bank and the second bit lines are located at a center of the second bank. ### Claim 35 (depends on 33) The resistive type memory device of claim 33, wherein the tiles of each bank are arranged in columns to form corresponding bays of tiles, wherein the first bit lines are arranged at corresponding edges of corresponding bays of the first bank and the second bit lines are arranged at central locations of corresponding bays of the second bank. ### Claim at position 14 36-59. (canceled) ### Claim 60 A method of storing data comprising: forming a first codeword from a first block of data; storing the first codeword in a resistive type memory device so that a first portion of the first codeword is stored in a first resistive type memory cells of the resistive type memory device and a second portion of the first codeword is stored in second resistive type memory cells of the resistive type memory device, the storing the first codeword in the resistive type memory device comprising: sending a write command to the resistive type memory device to store the first codeword in the resistive type memory device, sending a first memory address associated with the write command to the resistive type memory device, the memory address including a first row address and a first column address, and sending the first codeword to the resistive type memory device, wherein the first resistive type memory cells are identified by the first row address and first column address within a first bank of the resistive type memory device, wherein the second resistive type memory cells are identified by the first row address and first column address within a second bank of the resistive type memory device, and wherein the first resistive type memory cells have a first relative location with respect to the first bank, wherein the second resistive type memory cells have a second relative location with respect to the second bank, and wherein the first relative location is different from the second relative location. ### Claim 61 (depends on 60) The method of claim 60, wherein the first resistive type memory cells are connected to a first word line of the first bank that is identified by the first row address within the first bank, the first word line being formed at the first relative location with respect to the first bank, and wherein the second resistive type memory cells are connected to a second word line of the second bank that is identified by the first row address within the second bank, the second word line being formed at the second relative location with respect to the second bank. ### Claim 62 (depends on 61) The method of claim 61, wherein each of the first bank and the second bank comprise a plurality of resistive type memory cells organized in a plurality of tiles, the plurality of tiles of each bank being organized in a plurality of bays of tiles, wherein the first word line is located within a first tile of the first bank at a first relative location with respect to the first tile, wherein the second word line is located within a second tile of the second bank at a second relative location with respect to the second tile, and wherein the first relative location is different from the second relative location. ### Claim 63 (depends on 62) The method of claim 62, wherein the first relative location is located adjacent an edge of the first memory tile and the second relative location is centrally located within the second tile. ### Claim 64 (depends on 60) The method of claim 60, wherein the first resistive type memory cells are connected to a first set of bit lines of the first bank that is identified by the first column address within the first bank, and wherein the second resistive type memory cells are connected to a second set of bit lines of the second bank that is identified by the first column address within the second bank. ### Claim 65 (depends on 64) The method of claim 64, wherein each of the first bank and the second bank comprise a plurality of resistive type memory cells organized in a plurality of tiles, the plurality of tiles of each bank being organized in a plurality of bays of tiles, wherein the first set of bit lines are respectively located with corresponding bays at edges of the corresponding bays of the first bank, and wherein the second set of bit lines are centrally located within corresponding bays of the first bank. ### Claim 66 (depends on 60) The method of claim 60, further comprising: receiving information data from a host; dividing the information data into blocks of data, including the first block of data; performing error correction encoding operations on each of the blocks of data to generate a plurality of corresponding codewords, the plurality of codewords including the first codeword, each codeword including a corresponding one of the blocks of data and corresponding parity bits generated from a corresponding error correction encoding operation; and storing the plurality of codewords in the resistive type memory device so that first portions of each of the plurality of codewords are stored in the first bank of the resistive type memory device and second portions of each of the plurality of codewords are stored in the second bank, wherein, for each of the plurality of codewords, a relative location of resistive type memory cells storing the first portion of the codeword within the first bank is different from a relative location of resistive type memory cells storing the second portion of the codeword within the second bank. ### Claim 67 (depends on 66) The method of claim 66, wherein the first portion and second portion of each of the plurality of codewords is identified by a same corresponding row address and same corresponding column address.