# US 2019/0377631 A1 · Variable resistance random-access memory and method for write operation having error bit recovering function thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0377631 A1 - Document ID: US20190377631A1 - Status: Published application - Kind: A1 - Application number: 16/431,739 - Filed: 2019-06-05 - Published: 2019-12-12 - Earliest claimed: 2018-06-08 - Assignees: Winbond Electronics Corp. - Applicants: Winbond Electronics Corp. - Inventors: Norio Hattori - Web page: https://patentgrep.com/patent/US20190377631A1 ## CPC - G06F 11/1012: {using codes or arrangements adapted for a specific type of error (G06F11/1048 takes precedence)} - G06F 11/1048: {using arrangements adapted for a specific error detection or correction feature} - G11C 13/0026: {Bit-line or column circuits} - G11C 13/0028: {Word-line or row circuits} - G11C 13/0033: {Disturbance prevention or evaluation; Refreshing of disturbed memory data} - G11C 13/0035: {Evaluating degradation, retention or wearout, e.g. by counting writing cycles} - G11C 13/004: {Reading or sensing circuits or methods} - G11C 13/0064: {Verifying circuits or methods} - G11C 13/0069: {Writing or programming circuits or methods} - G11C 29/52: Protection of memory contents; Detection of errors in memory contents - G11C 2013/0073: {Write using bi-directional cell biasing} - G11C 2029/0411: {Online error correction} - G11C 2213/79: Array wherein the access device being a transistor - G11C 2213/82: Array having, for accessing a cell, a word line, a bit line and a plate or source line receiving different potentials - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Provided is a variable resistance random-access memory for suppressing degradation of performance by recovering a memory cell that fails. A variable resistance random-access memory of the disclosure includes a memory array, a row selection circuit, a column selection circuit, a controller, an error checking and correcting (ECC) circuit, an error bit flag register, and an error bit address register. The memory array includes a plurality of memory cells. The column selection circuit includes a sense amplifier and a write driver/read bias circuit. The error bit flag register stores bits for indicating presence/absence of an error bit in a write operation. The error bit address register stores an address of the error bit. The controller recovers the error bit when a predetermined event occurs. ## Claims ### Claim 1 A variable resistance random-access memory, comprising: a memory array comprising a plurality of memory cells; a controller configured to perform: writing a memory cell selected based on address information to be a predetermined resistance state; determining the written memory cell as pass if the written memory cell matches the predetermined resistance state or failure if the written memory cell does not match the predetermined resistance state; and recovering the written memory cell determined as failure based on the failure information when a predetermined event occurs; and a failure information holding element configured to hold failure information comprising an address of the written memory cell determined as failure. ### Claim 2 (depends on 1) The variable resistance random-access memory according to claim 1, wherein the predetermined resistance state is low resistance state, the failure information further comprises a bit for identification of the writing of SET, and the controller is configured to perform the recovering by rewriting of RESET and then rewriting of SET on the written memory cell determined as failure. ### Claim 3 (depends on 1) The variable resistance random-access memory according to claim 1, wherein the predetermined resistance state is high resistance state, the failure information further comprises a bit for identification of the writing of RESET, and the controller is configured to perform the recovering by rewriting of SET and then rewriting of RESET on the written memory cell determined as failure. ### Claim 4 (depends on 1) The variable resistance random-access memory according to claim 1, wherein the controller is further configured to determine the recovered memory cell as pass or failure, and if the recovered memory cell is determined as pass, the controller is further configured to clear the failure information held in the failure information holding element. ### Claim 5 (depends on 4) The variable resistance random-access memory according to claim 4, wherein the controller is further configured to repeat the recovering on the recovered memory cell determined as failure, and set the recovered memory cell determined as failure as unrecoverable and replace the unrecoverable memory cell with a redundant memory cell if the times of the recovering is equal to or greater than a preset value and the recovered memory cell still does not match the predetermined resistance state. ### Claim 6 (depends on 1) The variable resistance random-access memory according to claim 1, wherein the predetermined event is a read operation. ### Claim 7 (depends on 1) The variable resistance random-access memory according to claim 1, wherein the predetermined event is a write operation. ### Claim 8 (depends on 1) The variable resistance random-access memory according to claim 1, wherein the predetermined event is inputting of power. ### Claim 9 (depends on 1) The variable resistance random-access memory according to claim 1, wherein the controller is configured to perform the recovering in background of the predetermined event. ### Claim 10 (depends on 4) The variable resistance random-access memory according to claim 4, further comprising an error correction/detection circuit, wherein when the controller determines the recovered memory cell as failure and the error correction/detection circuit determines the number of the recovered memory cell determined as failure, the error correction/detection circuit is configure to execute error correction/detection on the recovered memory cell determined as failure if the number of the recovered memory cell determined as failure is not greater than a preset value. ### Claim 11 A method for a write operation having the error bit recovering function of a variable resistance random-access memory, the method comprising: writing a memory cell selected based on address information to be a predetermined resistance state; determining the written memory cell as pass if the written memory cell matches the predetermined resistance state or failure if the written memory cell does not match the predetermined resistance state; holding failure information comprising an address of the written memory cell determined as failure in a failure information holding element; and recovering the written memory cell determined as failure based on the failure information when a predetermined event occurs. ### Claim 12 (depends on 11) The method according to claim 11, wherein the predetermined resistance state is low resistance state, the failure information further comprises a bit for identification of the writing of SET, and the recovering includes rewriting of RESET and then rewriting of SET on the written memory cell determined as failure. ### Claim 13 (depends on 11) The method according to claim 11, wherein the predetermined resistance state is high resistance state, the failure information further comprises a bit for identification of the writing of RESET, and the recovering includes rewriting of SET and then rewriting of RESET on the written memory cell determined as failure. ### Claim 14 (depends on 11) The method according to claim 11, further comprising determining the recovered memory cell as pass or failure, and if the recovered memory cell is determined as pass, clearing the failure information held in the failure information holding element. ### Claim 15 (depends on 14) The method according to claim 14, further comprising repeating the recovering, setting the recovered memory cell determined as failure as unrecoverable and replacing the unrecoverable memory cell with a redundant memory cell, if the times of the recovering is equal to or greater than a preset value and the recovered memory cell still does not match the predetermined resistance state. ### Claim 16 (depends on 11) The method according to claim 11, wherein the predetermined event is a read operation. ### Claim 17 (depends on 11) The method according to claim 11, wherein the predetermined event is a write operation. ### Claim 18 (depends on 11) The method according to claim 11, wherein the predetermined event is inputting of power. ### Claim 19 (depends on 11) The method according to claim 11, wherein the recovering is performed in background of the predetermined event. ### Claim 20 (depends on 14) The method according to claim 14, wherein the variable resistance random-access memory further comprises an error correction/detection circuit, when the recovered memory cell is determined as failure and the method further comprises determining the number of the recovered memory cell determined as failure by the error correction/detection circuit, and executing error correction/detection on the recovered memory cell determined as failure by the error correction/detection circuit if the number of the recovered memory cell determined as failure is not greater than a preset value.