# US 2019/0377577 A1 · Dynamic adjustment of issue-to-issue delay between dependent instructions

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- Number: US 2019/0377577 A1
- Document ID: US20190377577A1
- Status: Published application
- Kind: A1
- Application number: 16/001,180
- Filed: 2018-06-06
- Published: 2019-12-12
- Earliest claimed: 2018-06-06
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Dongkook PARK; Ehsan FATEHI; Brian W. THOMPTO; Brian D. BARRICK
- Web page: https://patentgrep.com/patent/US20190377577A1

## CPC

- G06F 9/30145: {Instruction analysis, e.g. decoding, instruction word fields}
- G06F 9/321: {Program or instruction counter, e.g. incrementing}
- G06F 9/3826: {Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage}
- G06F 9/3836: {Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution}
- G06F 9/3858: {Result writeback, i.e. updating the architectural state or memory}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Systems, methods, and computer-readable media are described for dynamically adjusting the issue-to-issue delay among instructions in a dependency chain so as to minimize instruction issue delay due to write-back and/or broadcast collisions. The issue-to-issue delay between instructions is dynamically adjusted on-the-fly by disabling and enabling bypassing, thereby allowing the ISU to adapt to different instruction characteristics of various workloads executing on a processor, and as a result, minimize potential ISU broadcast and/or write-back collisions.

## Claims

### Claim 1

A computer-implemented method for dynamically adjusting an issue-to-issue delay mode of an instruction sequencing unit, the method comprising:
initializing the issue-to-issue delay mode to a bypassing mode;
identifying a plurality of instructions in an issue queue;
determining, for each of the plurality of instructions, whether the instruction is able to issue in the bypassing mode;
initializing a counter to a predetermined value;
decrementing the counter for each instruction able to issue in the bypassing mode;
incrementing the counter for each instruction not able to issue in the bypassing mode;
determining that the counter is greater than or equal to a threshold value; and
switching the issue-to-issue delay mode to a non-bypassing mode.

### Claim 2 (depends on 1)

The computer-implemented method of claim 1, further comprising determining that each of the plurality of instructions is a respective floating point instruction.

### Claim 3 (depends on 1)

The computer-implemented method of claim 1, wherein the counter is a first counter and the predetermined value is a first predetermined value, the method further comprising:
initializing a second counter to a second predetermined value;
determining that the issue-to-issue delay mode is set to the non-bypassing mode;
incrementing the second counter for each of one or more instruction cycles;
determining that the second counter equals a threshold reset value; and
switching the issue-to-issue delay mode back to the bypassing mode.

### Claim 4 (depends on 3)

The computer-implemented method of claim 3, further comprising resetting the first counter to a third predetermined value.

### Claim 5 (depends on 1)

The computer-implemented method of claim 1, further comprising:
identifying a critical instruction in the issue queue; and
switching the issue-to-issue delay mode to the bypassing mode such that the critical instruction can issue in the bypassing mode.

### Claim 6 (depends on 1)

The computer-implemented method of claim 1, wherein the plurality of instructions is a first plurality of instructions and the threshold value is a first threshold value, the method further comprising:
identifying a second plurality of instructions in the issue queue;
determining, for each of the second plurality of instructions, whether the instruction is able to issue in the bypassing mode;
decrementing the counter for each instruction in the second plurality of instructions that is able to issue in the bypassing mode;
incrementing the counter for each instruction in the second plurality of instructions that is not able to issue in the bypassing mode;
determining that the counter is equal to a second threshold value that is less than the first threshold value; and
switching the issue-to-issue delay mode back to the bypassing mode.

### Claim 7 (depends on 1)

The computer-implemented method of claim 1, wherein the plurality of instructions comprises at least two instructions having a source dependency there between.

### Claim 8

A system for dynamically adjusting an issue-to-issue delay mode of an instruction sequencing unit, the system comprising:
at least one processor, wherein the at least one processor comprises an instruction sequencing unit (ISU) that includes:
first hardware logic configured to:
initialize the issue-to-issue delay mode to a bypassing mode;
identify a plurality of instructions in an issue queue; and
determine, for each of the plurality of instructions, whether the instruction is able to issue in the bypassing mode; and
second hardware logic configured to:
initialize a counter to a predetermined value;
decrement the counter for each instruction able to issue in the bypassing mode;
increment the counter for each instruction not able to issue in the bypassing mode;
determine that the counter is greater than or equal to a threshold value; and
switch the issue-to-issue delay mode to a non-bypassing mode.

### Claim 9 (depends on 8)

The system of claim 8, wherein the first hardware logic is further configured to determine that each of the plurality of instructions is a respective floating point instruction.

### Claim 10 (depends on 8)

The system of claim 8, wherein the counter is a first counter and the predetermined value is a first predetermined value, and wherein the ISU further includes third hardware logic configured to:
initialize a second counter to a second predetermined value;
determine that the issue-to-issue delay mode is set to the non-bypassing mode;
increment the second counter for each of one or more instruction cycles;
determine that the second counter equals a threshold reset value; and
switch the issue-to-issue delay mode back to the bypassing mode.

### Claim 11 (depends on 10)

The system of claim 10, wherein the third hardware logic is further configured to reset the first counter to a third predetermined value.

### Claim 12 (depends on 8)

The system of claim 8, wherein the ISU further includes third hardware logic configured to:
identify a critical instruction in the issue queue; and
switch the issue-to-issue delay mode to the bypassing mode such that the critical instruction can issue in the bypassing mode.

### Claim 13 (depends on 8)

The system of claim 8, wherein the plurality of instructions is a first plurality of instructions and the threshold value is a first threshold value, wherein the ISU further includes third hardware logic configured to:
identify a second plurality of instructions in the issue queue;
determine, for each of the second plurality of instructions, whether the instruction is able to issue in the bypassing mode;
decrement the counter for each instruction in the second plurality of instructions that is able to issue in the bypassing mode;
increment the counter for each instruction in the second plurality of instructions that is not able to issue in the bypassing mode;
determine that the counter is equal to a second threshold value that is less than the first threshold value; and
switch the issue-to-issue delay mode back to the bypassing mode.

### Claim 14 (depends on 8)

The system of claim 8, wherein the plurality of instructions comprises at least two instructions having a source dependency there between.

### Claim 15

A computer program product for dynamically adjusting an issue-to-issue delay mode of an instruction sequencing unit, the computer program product comprising a storage medium readable by a processing circuit, the storage medium storing instructions executable by the processing circuit to cause a method to be performed, the method comprising:
initializing the issue-to-issue delay mode to a bypassing mode;
identifying a plurality of instructions in an issue queue;
determining, for each of the plurality of instructions, whether the instruction is able to issue in the bypassing mode;
initializing a counter to a predetermined value;
decrementing the counter for each instruction able to issue in the bypassing mode;
incrementing the counter for each instruction not able to issue in the bypassing mode;
determining that the counter is greater than or equal to a threshold value; and
switching the issue-to-issue delay mode to a non-bypassing mode.

### Claim 16 (depends on 15)

The computer program product of claim 15, the method further comprising determining that each of the plurality of instructions is a respective floating point instruction.

### Claim 17 (depends on 15)

The computer program product of claim 15, wherein the counter is a first counter and the predetermined value is a first predetermined value, the method further comprising:
initializing a second counter to a second predetermined value;
determining that the issue-to-issue delay mode is set to the non-bypassing mode;
incrementing the second counter for each of one or more instruction cycles;
determining that the second counter equals a threshold reset value; and
switching the issue-to-issue delay mode back to the bypassing mode.

### Claim 18 (depends on 17)

The computer program product of claim 17, the method further comprising resetting the first counter to a third predetermined value.

### Claim 19 (depends on 15)

The computer program product of claim 15, the method further comprising:
identifying a critical instruction in the issue queue; and
switching the issue-to-issue delay mode to the bypassing mode such that the critical instruction can issue in the bypassing mode.

### Claim 20 (depends on 15)

The computer program product of claim 15, wherein the plurality of instructions is a first plurality of instructions and the threshold value is a first threshold value, the method further comprising:
identifying a second plurality of instructions in the issue queue;
determining, for each of the second plurality of instructions, whether the instruction is able to issue in the bypassing mode;
decrementing the counter for each instruction in the second plurality of instructions that is able to issue in the bypassing mode;
incrementing the counter for each instruction in the second plurality of instructions that is not able to issue in the bypassing mode;
determining that the counter is equal to a second threshold value that is less than the first threshold value; and
switching the issue-to-issue delay mode back to the bypassing mode.