# US 2019/0377573 A1 · Element by vector operations in a data processing apparatus > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0377573 A1 - Document ID: US20190377573A1 - Status: Published application - Kind: A1 - Application number: 16/487,256 - Filed: 2018-02-02 - Published: 2019-12-12 - Earliest claimed: 2017-02-23 - Assignees: Arm Limited - Applicants: Arm Limited - Inventors: Grigorios MAGKLIS; Nigel John STEPHENS; Jacob EAPEN; Mbou EYOLE; David Hennah MANSELL - Web page: https://patentgrep.com/patent/US20190377573A1 ## CPC - G06F 9/3001: {Arithmetic instructions} - G06F 9/30036: {Instructions to perform operations on packed data, e.g. vector, tile or matrix operations} - G06F 9/30043: {LOAD or STORE instructions; Clear instruction} - G06F 9/30101: {Special purpose registers} - G06F 9/30109: {having multiple operands in a single register} - G06F 9/30112: {comprising data of variable length} - G06F 9/30145: {Instruction analysis, e.g. decoding, instruction word fields} - G06F 9/45541: {Bare-metal, i.e. hypervisor runs directly on hardware} - G06F 17/16: Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization (matrix transposition G06F7/78)} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A data processing apparatus, a method of operating a data processing apparatus, a non-transitory computer readable storage medium, and an instruction are provided. The instruction specifies a first source register, a second source register, and an index. In response to the instruction control signals are generated, causing processing circuitry to perform a data processing operation with respect to each data group in the first source register and the second source register to generate respective result data groups forming a result of the data processing operation. Each of the first source register and the second source register has a size which is an integer multiple at least twice a predefined size of the data group, and each data group comprises a plurality of data elements. The operands of the data processing operation for each data group are a selected data element identified in the data group of the first source register by the index and each data element in the data group of the second source register. A technique for element-by-vector operation which is readily scalable as the register width grows. ## Claims ### Claim 1 A data processing apparatus comprising: register storage circuitry having a plurality of registers; decoder circuitry responsive to a data processing instruction to generate control signals, the data processing instruction specifying in the plurality of registers: a first source register, a second source register, and an index, wherein each of the first source register and the second source register has a size which is an integer multiple at least twice a predefined size of a data group, and each data group comprises a plurality of data elements; and processing circuitry responsive to the control signals to perform a data processing operation with respect to each said data group in the first source register and the second source register to generate respective result data groups forming a result of the data processing operation, wherein operands of the data processing operation for each said data group are a selected data element identified in the data group of the first source register by the index and each data element in the data group of the second source register. ### Claim 2 (depends on 1) The data processing apparatus as claimed in claim 1, wherein the processing circuitry comprises data element manipulation circuitry responsive to the control signals to supply multiple instances of the selected data element to multiple data operation circuits, wherein each data operation circuit is responsive to the control signals to perform the data processing operation with respect to a respective data group in the first source register and the second source register. ### Claim 3 (depends on 1) The data processing apparatus as claimed in claim 1, wherein the decoder circuitry is responsive to a data preparation instruction to generate further control signals, the data preparation instruction specifying a memory location and a target register, and wherein the processing circuitry is responsive to the further control signals to retrieve a subject data group item having the predefined size from the memory location and to fill the target register by replication of the subject data group item. ### Claim 4 (depends on 3) The data processing apparatus as claimed in claim 3, wherein the target register is the first source register. ### Claim 5 (depends on 1) The data processing apparatus as claimed in claim 1, wherein the register storage circuitry comprises a control register to store an indication of the integer multiple. ### Claim 6 (depends on 5) The data processing apparatus as claimed in claim 5, wherein the decoder circuitry is responsive to a control instruction to amend the indication of the integer multiple up to a predefined maximum value for the data processing apparatus. ### Claim 7 (depends on 1) The data processing apparatus as claimed in claim 1, wherein the data processing instruction further specifies a result register in the plurality of registers, and the processing circuitry is further responsive to the control signals to apply the result of the data processing operation to the result register. ### Claim 8 (depends on 7) The data processing apparatus as claimed in claim 7, wherein the processing circuitry is responsive to the control signals to store the result of the data processing operation in the result register. ### Claim 9 (depends on 1) The data processing apparatus as claimed in claim 1, wherein the processing circuitry is responsive to the control signals to apply the result of the data processing operation to the second source register. ### Claim 10 (depends on 1) The data processing apparatus as claimed in claim 1, wherein the data processing instruction further specifies at least one further source register in the plurality of registers, wherein the processing circuitry is responsive to the control signals to perform the data processing operation with further respect to each said data group in the at least one further source register to generate the respective result data groups forming the result of the data processing operation, and wherein operands of the data processing operation for each said data group further comprise each data element in the data group of the at least one further source register. ### Claim 11 (depends on 10) The data processing apparatus as claimed in claim 10, wherein the processing circuitry is responsive to the control signals to accumulate the result of the data processing operation with previous content in the at least one further source register. ### Claim 12 (depends on 1) The data processing apparatus as claimed in claim 1, wherein the data processing operation is an arithmetic operation. ### Claim 13 (depends on 12) The data processing apparatus as claimed in claim 12, wherein the data processing operation is a multiply operation. ### Claim 14 (depends on 8, 12) The data processing apparatus as claimed in claim 12, when dependent on claim 8, wherein the data processing operation is a dot product operation comprising: extracting at least a first data element and a second data element from each of the first source register and the second source register; performing multiply operations of multiplying together at least first data element pairs and second data element pairs; and summing results of the multiply operations. ### Claim 15 (depends on 14) The data processing apparatus as claimed in claim 14, wherein the multiply operations comprise multiplying together first data element pairs, second data element pairs, third data element pairs and fourth data element pairs. ### Claim 16 (depends on 14) The data processing apparatus as claimed in claim 14, wherein the data processing instruction further specifies an accumulation register in the plurality of registers and the data processing operation is a dot product and accumulate operation which further comprises: loading an accumulator value from the accumulator register; summing the results of the multiply operations with the accumulator value; and storing a result of the summing to the accumulator register. ### Claim 17 (depends on 8) The data processing apparatus as claimed in claim 8, wherein the data processing operation is an arithmetic operation and the data processing operation is a multiply-accumulate operation. ### Claim 18 (depends on 17) The data processing apparatus as claimed in claim 17, wherein the data element in each said data group in the first source register and the second source register is a pair of data values representing a complex number and the data processing operation is a multiply-accumulate of complex numbers. ### Claim 19 (depends on 18) The data processing apparatus as claimed in claim 18, wherein the data processing instruction further specifies a rotation parameter, wherein the processing circuitry is responsive to the rotation parameter to perform the multiply-accumulate of complex numbers using a selected permutation the data values and their signs which are subject to the data processing operation. ### Claim 20 (depends on 1) The data processing apparatus as claimed in claim 1, wherein the data processing operation is a logical operation. ### Claim 21 A method of data processing comprising: decoding a data processing instruction to generate control signals, the data processing instruction specifying in a plurality of registers: a first source register, a second source register, and an index, wherein each of the first source register and the second source register has a size which is an integer multiple at least twice a predefined size of a data group, and each data group comprises a plurality of data elements; and performing a data processing operation in response to the control signals with respect to each said data group in the first source register and the second source register to generate respective result data groups forming a result of the data processing operation, wherein operands of the data processing operation for each said data group are a selected data element identified in the data group of the first source register by the index and each data element in the data group of the second source register. ### Claim 22 A computer-readable storage medium storing in a non-transient fashion a program comprising at least one data processing instruction which when executed by a data processing apparatus causes: generation of control signals in response to the data processing instruction, the data processing instruction specifying in a plurality of registers: a first source register, a second source register, and an index, wherein each of the first source register and the second source register has a size which is an integer multiple at least twice a predefined size of a data group, and each data group comprises a plurality of data elements; and performance of a data processing operation in response to the control signals with respect to each said data group in the first source register and the second source register to generate respective result data groups forming a result of the data processing operation, wherein operands of the data processing operation for each said data group are a selected data element identified in the data group of the first source register by the index and each data element in the data group of the second source register. ### Claim 23 (canceled) ### Claim 24 (depends on 1) A virtual machine provided by a computer program executing upon a data processing apparatus, said virtual machine providing an instruction execution environment corresponding to the data processing apparatus of claim 1.