# US 2019/0377549 A1 · Stochastic rounding of numerical values

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- Number: US 2019/0377549 A1
- Document ID: US20190377549A1
- Status: Published application
- Kind: A1
- Application number: 16/001,838
- Filed: 2018-06-06
- Published: 2019-12-12
- Earliest claimed: 2018-06-06
- Assignees: NVIDIA Corporation
- Applicants: NVIDIA Corporation
- Inventors: Jonah M. Alben; Paulius Micikevicius; Hao Wu; Ming Yiu Siu
- Web page: https://patentgrep.com/patent/US20190377549A1

## CPC

- G06F 7/49947: {Rounding}
- G06F 7/49957: {Implementation of IEEE-754 Standard}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A method, computer readable medium, and system are disclosed for rounding numerical values. A set of bits from an input value is identified as a rounding value. A second set of bits representing a second value is extracted from the input value and added with the rounding value to produce a sum. The sum is truncated to produce the rounded output value. Thus, the present invention provides a stochastic rounding technique that rounds up an input value as a function of a second value and a rounding value, both of which were obtained from the input value. When the second value and rounding value are obtained from consistent bit locations of the input value, the resulting output value is deterministic. Stochastic rounding, which is deterministic, is advantageously applicable in deep learning applications.

## Claims

### Claim 1

A circuit, configured to:
receive an input value represented by a first number of bits;
identify a portion of the first number of bits of the input value as a rounding value represented by a second number of bits;
extract a second value from the input value;
align the rounding value with a rounding position within the second value, wherein the rounding position corresponds to a least significant bit of an output value represented by a third number of bits;
add the aligned rounding value and the second value to produce a sum; and
truncate a fourth number of bits from the sum to produce the output value.

### Claim 2 (depends on 1)

The circuit of claim 1, wherein the third number of bits is less than the first number of bits.

### Claim 3 (depends on 1)

The circuit of claim 1, wherein a fraction value replaces the rounding value when the input value is greater than a threshold value.

### Claim 4 (depends on 1)

The circuit of claim 1, wherein the input value is a mantissa of a floating-point format number.

### Claim 5 (depends on 1)

The circuit of claim 1, wherein the second number bits and the fourth number of bits are the same.

### Claim 6 (depends on 3)

The circuit of claim 3, wherein the fraction value is one of a fixed value, a programmed value, and a computed value.

### Claim 7 (depends on 1)

The circuit of claim 1, wherein a fraction value replaces the rounding value when the input value is within a threshold range.

### Claim 8 (depends on 1)

The circuit of claim 1, wherein a fraction value replaces the rounding value based on a rounding mode.

### Claim 9 (depends on 1)

The circuit of claim 1, wherein, prior to aligning the rounding value, the rounding value is modified based on a fraction value that is one of a fixed value, a programmed value, or a computed value.

### Claim 10 (depends on 9)

The circuit of claim 9, wherein the rounding value is bitwise exclusive ORed with the fraction value.

### Claim 11 (depends on 9)

The circuit of claim 9, wherein the rounding value is bitwise rotated according to the fraction value.

### Claim 12 (depends on 9)

The circuit of claim 9, wherein the rounding value is bitwise ANDed with the fraction value.

### Claim 13 (depends on 1)

The circuit of claim 1, wherein the rounding value comprises the second number of least significant bits of the input value.

### Claim 14 (depends on 13)

The circuit of claim 13, wherein the second number of bits is eight.

### Claim 15 (depends on 1)

The circuit of claim 1, wherein the input value is a mantissa of a floating-point format number and the output value is an integer.

### Claim 16 (depends on 1)

The circuit of claim 1, wherein at least one of the input value, the first number of bits, the second number of bits, and the third number of bits is included as an operand of a conversion instruction.

### Claim 17 (depends on 16)

The circuit of claim 16, wherein the instruction is a format conversion instruction.

### Claim 18 (depends on 16)

The circuit of claim 16, wherein the instruction is an arithmetic operation instruction.

### Claim 19

A method, comprising:
receiving an input value represented by a first number of bits;
identifying a portion of the first number of bits of the input value as a rounding value represented by a second number of bits;
extracting a second value from the input value;
aligning the rounding value with a rounding position within the second value, wherein the rounding position corresponds to a least significant bit of an output value represented by a third number of bits;
adding the aligned rounding value and the second value to produce a sum; and
truncating a fourth number of bits from the sum to produce the output value.

### Claim 20

A non-transitory, computer-readable storage medium storing instructions that, when executed by a processing unit, cause the processing unit to:
receive an input value represented by a first number of bits;
identify a portion of the first number of bits of the input value as a rounding value represented by a second number of bits;
extract a second value from the input value;
align the rounding value with a rounding position within the second value, wherein the rounding position corresponds to a least significant bit of an output value represented by a third number of bits;
add the aligned rounding value and the second value to produce a sum; and
truncate a fourth number of bits from the sum to produce the output value.