# US 2019/0377404 A1 · Compute through power loss hardware approach for processing device having nonvolatile logic memory

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- Number: US 2019/0377404 A1
- Document ID: US20190377404A1
- Status: Published application
- Kind: A1
- Application number: 16/451,260
- Filed: 2019-06-25
- Published: 2019-12-12
- Earliest claimed: 2015-12-29
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Michael Zwerg; Steven Craig Bartling; Sudhanshu Khanna
- Web page: https://patentgrep.com/patent/US20190377404A1

## CPC

- G06F 1/3293: by switching to a less power-consuming processor, e.g. sub-CPU
- G06F 1/3206: Monitoring of events, devices or parameters that trigger a change in power modality
- G06F 1/3287: by switching off individual functional units in the computer system
- G06F 3/061: {Improving I/O performance}
- G06F 3/0625: {Power saving in storage systems}
- G06F 3/0634: {by changing the state or mode of one or more devices}
- G06F 3/0655: {Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices}
- G06F 3/0656: {Data buffering arrangements}
- G06F 3/0688: {Non-volatile semiconductor memory arrays}
- G06F 11/07: Responding to the occurrence of a fault, e.g. fault tolerance
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- Y02D 30/50: in wire-line communication networks, e.g. low power modes or reduced link rate
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A computing device apparatus facilitates use of a deep low power mode that includes powering off the device's CPU by including a hardware implemented process to trigger storage of data from the device's volatile storage elements in non-volatile memory in response to entering the low power mode. A hardware based power management unit controls the process including interrupting a normal processing order of the CPU and triggering the storage of the data in the non-volatile memory. In response to a wake-up event, the device is triggered to restore the data stored in the non-volatile memory to the volatile memory prior to execution of a wake up process for the CPU from the low power mode. The device includes a power storage element such as a capacitor that holds sufficient energy to complete the non-volatile data storage task prior to entering the low power mode.

## Claims

### Claim 1

An electronic device comprising:
a central processing unit;
a power management unit configured to detect multiple levels of available power for the central processing unit and to effect switching power on or off for the central processing unit;
an energy storage unit connected to provide power to the electronic device and configured to hold enough energy to operate the electronic device after removal of power from the electronic device;
a non-volatile memory; and
a non-volatile memory controller configured to control the non-volatile memory and have direct access to volatile storage elements embedded in or associated with one or more of the central processing unit or one or more peripherals;
wherein the power management unit is configured to:
interrupt a normal processing order of the central processing unit to effect entry of the central processing unit into a low power mode in response to detecting a power loss event initiated by the power management unit due to detection of a power loss scenario or initiated by the central processing unit to save energy, the low power mode being a mode in which data stored in the volatile storage elements is transferred to the non-volatile memory and supply of power to the volatile storage elements is stopped thereafter;
use energy stored in the energy storage device to:
in response to entering into the low power mode, trigger the non-volatile memory controller to perform a save operation to store data stored in the volatile storage elements in the non-volatile memory, the data representing a state of the one or more of the central processing unit or one or more peripherals, and, after the data is saved in the non-volatile memory, effect switching off power to the central processing unit and the volatile storage elements;
during the low power mode, detect restoration of power to the electronic device or a wakeup request from the central processing unit's power off state; and
in response to detecting the restoration of power or the wakeup request, exit the low power mode by supplying power to the volatile storage elements and triggering the non-volatile memory controller to perform a restore operation to restore the data from the non-volatile memory to the volatile storage elements prior to execution of a wake up process for the central processing unit from the low power mode;
wherein the power management unit is further configured to prevent a startup of the electronic device while in the low power mode unless enough energy is present on the energy storage unit to complete a round trip of a restore operation in which the low power mode is exited followed by a save operation in which the low power mode is entered again.

### Claim 2 (depends on 1)

The electronic device of claim 1, wherein the non-volatile memory has a high write cycle endurance of 1010.

### Claim 3 (depends on 1)

The electronic device of claim 1, wherein the non-volatile memory controller is configured to not store bus interface state information for the central processing unit in response to entering the low power mode.

### Claim 4 (depends on 1)

The electronic device of claim 1, wherein the non-volatile memory controller is configured to not store serial communication module information for the central processing unit in response to entering the low power mode.

### Claim 5 (depends on 1)

The electronic device of claim 1, wherein the non-volatile memory controller is configured to not store state machine information for the central processing unit in response to entering the low power mode.

### Claim 6 (depends on 1)

The electronic device of claim 1, wherein the non-volatile memory controller is configured to not store pipeline register information for the central processing unit or the one or more peripherals in response to entering the low power mode.

### Claim 7 (depends on 1)

The electronic device of claim 1, wherein the central processing unit and the power management unit are configured to not automatically trigger execution of a cold boot initialization process in response to the detecting the restoration of power or the wake up request.

### Claim 8 (depends on 1)

The electronic device of claim 1, wherein the non-volatile memory controller is configured to effect storing the data of the central processing unit by storing one or more of program counters, stack pointers, status registers, general purpose registers, or other key state information of the central processing unit.

### Claim 9 (depends on 1)

The electronic device of claim 1, wherein the non-volatile memory controller is configured to effect storing the data of the one or more peripherals associated with the central processing unit by storing one or more of peripheral configuration registers, peripheral state registers, peripheral status registers, peripheral data buffers, and other key peripheral state information.