# US 2019/0377378 A1 · Low latency combined clock data recovery logic network and charge pump circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0377378 A1 - Document ID: US20190377378A1 - Status: Published application - Kind: A1 - Application number: 16/439,483 - Filed: 2019-06-12 - Published: 2019-12-12 - Earliest claimed: 2018-06-12 - Assignees: Kandou Labs, S.A. - Applicants: Kandou Labs, S.A. - Inventors: Kiarash Gharibdoust - Web page: https://patentgrep.com/patent/US20190377378A1 ## CPC - H03L 7/0807: {concerning mainly a recovery circuit for the reference signal} - G06F 1/10: Distribution of clock signals {, e.g. skew} - H03K 19/20: characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) - H03L 7/085: concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00) - H03L 7/0891: {the up-down pulses controlling source and sink current generators, e.g. a charge pump} - H03M 1/1255: {Synchronisation of the sampling frequency or phase to the input frequency or phase} - H04L 25/03057: {with a recursive structure (H04L25/03031 takes precedence)} - H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract Methods and systems are described for obtaining a sequence of data decisions and an error signal generated by one or more samplers operating on a received input signal according to a sampling clock, applying the sequence of data decisions and the error signal to each logic branch of a set of logic branches, and responsively selecting a logic branch from the set of logic branches, the logic branch selected responsive to (i) a detection of a transitional data pattern in the sequence of data decisions and (ii) the error signal, the selected logic branch generating an output current, and providing the output current to a local oscillator controller, the output current sourcing and sinking current to a capacitor through a resistive element to adjust an input voltage of a proportional control circuit relative to a voltage on the capacitor connected to the resistive element. ## Claims ### Claim 1 A method comprising: obtaining a sequence of data decisions from a history buffer and an error signal, the sequence of data decisions and the error signal generated by one or more samplers operating on a received input signal according to a sampling clock; applying the sequence of data decisions and the error signal to each logic branch of a set of logic branches, and responsively selecting a logic branch from the set of logic branches, the logic branch selected responsive to (i) a detection of a transitional data pattern in the sequence of data decisions and (ii) the error signal, the selected logic branch generating an output current; and providing the output current to a local oscillator controller to adjust an input voltage of a proportional control circuit, the output current sourcing and sinking current to a capacitor through a resistive element to adjust the input voltage of the proportional control circuit relative to a voltage on the capacitor connected to the resistive element. ### Claim 2 (depends on 1) The method of claim 1, further comprising adjusting an input voltage of an integral control circuit. ### Claim 3 (depends on 2) The method of claim 2, wherein adjusting the input voltage of the integral control circuit comprises sourcing and sinking a portion of the output current to a second capacitor via a second resistive element. ### Claim 4 (depends on 3) The method of claim 3, wherein the input voltage of the integral control circuit is adjusted responsive to a change in the voltage on the capacitor connected to the resistive element. ### Claim 5 (depends on 2) The method of claim 2, wherein adjusting the input voltage of the integral control circuit comprises generating an analog voltage using a digital-to-analog converter (DAC). ### Claim 6 (depends on 5) The method of claim 5, wherein the analog voltage is generated from accumulating error signals in a multi-bit register. ### Claim 7 (depends on 1) The method of claim 1, wherein the sequence of data decisions and the error signal are applied to each logic branch via respective sets of series-connected transistors in the logic branch. ### Claim 8 (depends on 1) The method of claim 1, wherein the sequence of data decisions and error signal are obtained from samplers applying speculative DFE correction values to the received input signal. ### Claim 9 (depends on 1) The method of claim 1, wherein the received input signal corresponds to an output of a multi-input comparator. ### Claim 10 (depends on 1) The method of claim 1, wherein the received input signal corresponds to one data phase of a plurality of data phases. ### Claim 11 An apparatus comprising: one or more samplers configured to operate on a received input signal according to a sampling clock, the one or more samplers further configured to generate a sequence of data decisions obtained from a history buffer and an error signal; a set of logic branches, each logic branch receiving the sequence of data decisions and the error signal, each logic branch from the set of logic branches configured to be selected in accordance with the sequence of data decisions and the error signal responsive to (i) a detection of a transitional data pattern in the sequence of data decisions and (ii) the error signal, the selected logic branch configured to generate an output current; and a local oscillator controller configured to receive the output current and to adjust an input voltage of a proportional control circuit, the output current sourcing and sinking current to a capacitor through a resistive element to adjust the input voltage of the proportional control circuit relative to a voltage on the capacitor connected to the resistive element. ### Claim 12 (depends on 11) The apparatus of claim 11, further comprising an integral control circuit, and wherein the local oscillator controller is configured to adjust an input voltage to the integral control circuit. ### Claim 13 (depends on 12) The apparatus of claim 12, wherein the local oscillator controller is configured to adjust the input voltage of the integral control circuit by sourcing and sinking a portion of the output current to a second capacitor via a second resistive element. ### Claim 14 (depends on 13) The apparatus of claim 13, wherein the input voltage of the integral control circuit is adjusted responsive to a change in the voltage on the capacitor connected to the resistive element. ### Claim 15 (depends on 12) The apparatus of claim 12, wherein the local oscillator controller comprises a digital-to-analog converter (DAC) configured to adjust the input voltage of the integral control circuit ### Claim 16 (depends on 15) The apparatus of claim 15, wherein the DAC comprises a multi-bit register configured to accumulate error signals to adjust the input voltage of the integral control circuit. ### Claim 17 (depends on 11) The apparatus of claim 11, wherein each logic branch comprises a respective set of series-connected transistors configured to receive the sequence of data decisions and the error signal. ### Claim 18 (depends on 11) The apparatus of claim 11, wherein the one or more sampler are configured to apply speculative DFE correction values to the received input signal. ### Claim 19 (depends on 11) The apparatus of claim 11, further comprising a multi-input comparator configured to generate the received input signal. ### Claim 20 (depends on 11) The apparatus of claim 11, wherein the received input signal corresponds to one data phase of a plurality of data phases.