Plc, network unit, cpu, and data transfer method

A central processing unit (CPU) configured to send and receive data via a shared memory to and from network circuitry, the network circuitry and the CPU being included in a programmable logic controller (PLC), the CPU comprising:

• a storage;
• a first transferrer to read first data from the shared memory and transfer the first data to the storage at an interval of a first transfer period when a flag is set indicating that a read from the shared memory is allowed, the first data being data for which data consistency is to be guaranteed among data stored in the shared memory;
• and
• a second transferrer to read second data from the shared memory and transfer the second data to the storage at an interval of a second transfer period that is different from the first transfer period, the second data being data for which real-timeliness is to be guaranteed among the data stored in the shared memory.

A data transfer method for transferring data between a central processing unit (CPU) and network circuitry via a shared memory readable and writable by the CPU and the network circuitry, the CPU and the network circuitry being included in a programmable logic controller (PLC), the data transfer method comprising:

• recording, by the network circuitry, first data in the shared memory when a flag is set indicating that a write to the shared memory is allowed, the first data being data for which data consistency is to be guaranteed among received data that is received from a device connected via a network,
• recording, by the network circuitry, second data in the shared memory, the second data being data for which real-timeliness is to be guaranteed among the received data,
• reading, by the CPU, the first data from the shared memory and transferring, by the CPU, the first data to a storage of the CPU at an interval of a first transfer period when the flag is set indicating that a read from the shared memory is allowed, and
• reading, by the CPU, the second data from the shared memory and transferring, by the CPU, the second data to the storage at an interval of a second transfer period that is different from the first transfer period.