# US 2019/0377232 A1 · Active matrix substrate and method for manufacturing the same

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2019/0377232 A1
- Document ID: US20190377232A1
- Status: Published application
- Kind: A1
- Application number: 16/432,221
- Filed: 2019-06-05
- Published: 2019-12-12
- Earliest claimed: 2018-06-12
- Assignees: Sharp Kabushiki Kaisha
- Applicants: Sharp Kabushiki Kaisha
- Inventors: Hidenobu KIMOTO
- Web page: https://patentgrep.com/patent/US20190377232A1

## CPC

- G02F 1/134363: {for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]}
- H10D 30/6737: {characterised by the electrode materials}
- G02F 1/13439: {characterised by their electrical, optical, physical properties; materials therefor; method of making}
- G02F 1/136286: {Wiring, e.g. gate line, drain line}
- G02F 1/1368: in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)}
- H10D 30/6743: {Silicon}
- H10D 86/021: {of multiple TFTs}
- H10D 86/0231: {using masks, e.g. half-tone masks}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/451: {characterised by the compositions or shapes of the interlayer dielectrics}
- H10D 86/60: wherein the TFTs are in active matrices
- H10P 50/642: {Chemical etching}
- H10P 50/667: {by liquid etching only}
- G02F 1/133707: {Structures for producing distorted electric fields, e.g. bumps, protrusions, recesses, slits in pixel electrodes}
- G02F 1/134318: {having a patterned common electrode}
- G02F 1/13625: {Patterning using multi-mask exposure}
- G02F 1/136295: {Materials; Compositions; Manufacture processes}
- G02F 2202/103: a-Si
- H10D 30/0316: {of lateral bottom-gate TFTs comprising only a single gate}
- H10D 30/0321: {comprising silicon, e.g. amorphous silicon or polysilicon}
- H10D 30/6732: {Bottom-gate only TFTs}
- H10D 30/6746: {Amorphous silicon}
- H10D 64/693: {the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials}
- H10P 14/24: using chemical vapour deposition [CVD]
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3454: {Amorphous}
- H10P 14/418: {the conductive layers comprising transition metals}
- H10P 14/69433: {the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz}
- H10P 76/2041: {Photolithographic processes}
- G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

An active matrix substrate of a liquid crystal panel of an FFS mode includes gate lines, data lines, pixel circuits each including a switching element and a pixel electrode, a protective insulating film formed in a layer over these elements, and a common electrode formed in a layer over the protective insulating film. The data line includes a lower layer conductor part formed using indium tin oxide together with the pixel electrode, and an upper layer conductor part formed using molybdenum niobium and an aluminum alloy. The lower layer conductor part is formed in a disconnected shape at a position of the switching element, and the upper layer conductor part is formed in a continuous shape so as to overlap with the lower layer conductor part. With this, an active matrix substrate capable of preventing a disconnection failure of the data line and an alignment failure is provided.

## Claims

### Claim 1

An active matrix substrate comprising:
gate lines;
data lines;
pixel circuits arranged corresponding to intersections of the gate lines and the data lines and each including a switching element and a pixel electrode;
a protective insulating film formed in a layer over the gate line, the data line, the switching element, and the pixel electrode; and
a common electrode formed in a layer over the protective insulating film, wherein
the data line includes a lower layer conductor part formed using indium tin oxide together with the pixel electrode, and an upper layer conductor part formed using a metal material other than indium tin oxide,
the lower layer conductor part is formed in a disconnected shape at a position of the switching element, and
the upper layer conductor part is formed in a continuous shape so as to overlap with the lower layer conductor part.

### Claim 2 (depends on 1)

The active matrix substrate according to claim 1, wherein the lower layer conductor part is formed in a disconnected shape at an arrangement position of the gate line.

### Claim 3 (depends on 1)

The active matrix substrate according to claim 1, wherein the upper layer conductor part is formed using molybdenum niobium and an aluminum alloy.

### Claim 4 (depends on 3)

The active matrix substrate according to claim 3, wherein the upper layer conductor part has a three-layer structure including molybdenum niobium, the aluminum alloy, and molybdenum niobium.

### Claim 5 (depends on 1)

The active matrix substrate according to claim 1, wherein the upper layer conductor part is formed so as to have a line width narrower than that of the lower layer conductor part.

### Claim 6 (depends on 1)

The active matrix substrate according to claim 1, wherein the common. electrode has slits corresponding to the pixel electrode.

### Claim 7

A method for manufacturing an active matrix substrate, comprising:
forming gate lines and gate electrodes of switching elements in a first wiring layer;
forming a gate insulating film and a semiconductor film;
forming a pixel electrode layer by forming pixel electrodes and lower layer conductor parts of data lines in the pixel electrode layer using indium tin oxide;
forming a source layer by forming upper layer conductor parts of the data lines and conduction electrodes of the switching elements in a second wiring layer using a metal material other than indium tin oxide and patterning the semiconductor film;
forming a protective insulating film in a layer over the pixel electrode; and.
forming a common electrode in a layer over the protective insulating film, wherein
in forming the pixel electrode laver, the lower layer conductor part is formed. in a disconnected shape at a position of the switching element, and.
in forming the source layer, the upper layer conductor part is formed in a continuous shape so as to overlap with the lower layer conductor part.

### Claim 8 (depends on 7)

The method for manufacturing the active matrix substrate according to claim 7, wherein in forming the pixel electrode layer, the lower layer conductor part is formed in a disconnected shape at an arrangement position of the gate line.

### Claim 9 (depends on 7)

The method for manufacturing the active matrix substrate according to claim 7, wherein in forming the source layer, the upper layer conductor part and the conduction electrode are formed using molybdenum niobium and an aluminum alloy.

### Claim 10 (depends on 9)

The method for manufacturing the active matrix substrate according to claim 9, wherein in forming the source layer, the upper layer conductor part and the conduction electrode are formed so as to have a three-layer structure including molybdenum niobium, the aluminum alloy, and molybdenum niobium,

### Claim 11 (depends on 7)

The method for manufacturing the active matrix substrate according to claim 7, wherein
in forming the pixel electrode layer, etching is performed us rig ferric chloride or oxalic acid, and
in forming the source layer, etching is performed using an etching solution which does not etch indium tin oxide.

### Claim 12 (depends on 11)

The method for manufacturing the active matrix substrate according to claim 11, wherein in forming the source layer, etching is performed using phosphoric-nitric-acetic acid.

### Claim 13 (depends on 7)

The method for manufacturing the active matrix substrate according to claim 7, wherein in forming the source layer, the upper layer conductor part. is formed so as to have a line width narrower than that of the lower layer conductor part.

### Claim 14 (depends on 7)

The method for manufacturing the active matrix substrate according to claim 7, wherein in forming the common electrode, the common electrode is formed so as to have slits corresponding to the pixel electrode.