# US 2019/0377076 A1 · Phase preset for fast chirp pll

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- Number: US 2019/0377076 A1
- Document ID: US20190377076A1
- Status: Published application
- Kind: A1
- Application number: 16/426,638
- Filed: 2019-05-30
- Published: 2019-12-12
- Earliest claimed: 2018-06-06
- Assignees: NXP USA, Inc.
- Applicants: NXP USA, Inc.
- Inventors: Jean-Stephane Vigier; Didier Salle; Cristian Pavao-Moreira; Julien Orlando
- Web page: https://patentgrep.com/patent/US20190377076A1

## CPC

- G01S 7/032: {Constructional details for solid-state radar subsystems}
- G01S 13/343: {using sawtooth modulation}
- G01S 7/35: Details of non-pulse systems
- G01S 7/4008: {of transmitters}
- G01S 13/34: using transmission of continuous, frequency-modulated waves while heterodyning the received signal, or a signal derived therefrom, with a locally-generated signal related to the contemporaneously transmitted signal
- H03B 1/04: Reducing undesired oscillations, e.g. harmonics
- H03C 3/0925: {applying frequency modulation at the divider in the feedback loop}
- H03C 3/0991: {including calibration means or calibration methods}
- H03L 7/087: using at least two phase detectors or a frequency and phase detector in the loop
- H03L 7/18: using a frequency divider or counter in the loop (H03L7/20, H03L7/22 take precedence)
- H03L 7/22: using more than one loop
- G01S 13/282: {using a frequency modulated carrier wave (G01S13/286 takes precedence)}
- G01S: RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- H03B: GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS (generators adapted for electrophonic musical instruments G10H; masers or lasers H01S; generation of oscillations in plasma H05H)
- H03C: MODULATION (masers or lasers H01S; coding, decoding or code conversion H03M)
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)

## Abstract

A fast chirp Phase Locked Loop (70) with a phase preset includes a Voltage Controlled Oscillator, VCO, (12) generating a Frequency Modulated Continuous Waveform, FMCW, (14). The VCO responds to a filtered output voltage (74) of a filter (72) connected to a charge pump (28). A digital controller (82) modifies the FMCW to generate a chirp phase (304) and a return phase (300). The chirp phase includes a first linear change of the FMCW from a start frequency (202) to a stop frequency (204). The return phase includes a second linear change of the FMCW from the stop frequency to the start frequency. A phase preset circuit (86) connects to the digital controller and the filter. The phase preset circuit supplies a phase preset current (98) during a start frequency time (302) preceding the chirp phase. The phase preset current is proportional to a VCO gain of the VCO and inversely proportional to a chirp current during the chirp phase.

## Claims

### Claim 1

A fast chirp Phase Locked Loop, PLL, with phase preset comprising:
a Voltage Controlled Oscillator, VCO, configured to generate a Frequency Modulated Continuous Waveform, FMCW, the VCO responsive to a filtered output voltage of a filter connected to a charge pump, the charge pump responsive to a difference between a reference frequency waveform and a divided frequency waveform generated by a frequency divider configured to divide the FMCW;
a digital controller connected to the frequency divider and configured to modify a division ratio of the frequency divider to generate a chirp phase and a return phase, the chirp phase including a first linear change of the FMCW from a start frequency to a stop frequency, and the return phase including a second linear change of the FMCW from the stop frequency to the start frequency; and
a phase preset circuit connected to the digital controller and the filter, the phase preset circuit supplying a phase preset current during a start frequency time preceding the chirp phase, the phase preset current proportional to a VCO gain of the VCO and inversely proportional to a chirp current during the chirp phase.

### Claim 2 (depends on 1)

The PLL of claim 1 wherein the phase preset current is determined by a calibration circuit including a counter configured to determine a number of clock cycles elapsed during a change from the stop frequency to the start frequency by measuring the filtered output voltage, storing the number of clock cycles in the digital controller and controlling the phase preset circuit with the digital controller to supply the phase preset current.

### Claim 3 (depends on 2)

The PLL of claim 2 wherein the phase preset current is determined by multiplying a calibration current, supplied by the phase preset circuit to the filter, by the number of clock cycles, multiplied by a clock period, and divided by a duration of the chirp phase.

### Claim 4 (depends on 1)

The PLL of claim 1 wherein the filter is a low pass filter comprising a plurality of filter stages.

### Claim 5 (depends on 4)

The PLL of claim 4 wherein the phase preset current is distributed to each of the plurality of filter stages.

### Claim 6 (depends on 1)

The PLL of claim 1 wherein, without the phase preset current, the PLL has a reduction in a usable chirp phase.

### Claim 7

A method for presetting a phase of a fast chirp Phase Locked Loop, PLL, comprising:
generating a Frequency Modulated Continuous Waveform, FMCW, with a Voltage Controlled Oscillator, VCO, the VCO responding to a filtered output voltage;
dividing the FMCW, with a frequency divider, to generate a divided frequency waveform;
generating a charge pump voltage in response to a difference between a reference frequency waveform and the divided frequency waveform;
filtering the charge pump voltage with a filter, to generate the filtered output voltage;
modifying, with a digital controller, a division ratio of the frequency divider to generate a chirp phase and a return phase, the chirp phase including a first linear change of the FMCW from a start frequency to a stop frequency, and the return phase including a second linear change of the FMCW from the stop frequency to the start frequency; and
supplying, with a phase preset circuit, a phase preset current to the filter during a start frequency time preceding the chirp phase, wherein the phase preset current is proportional to a VCO gain of the VCO and inversely proportional to a chirp current during the chirp phase.

### Claim 8 (depends on 7)

The method of claim 7 further comprising determining the phase preset current by counting, with a calibration circuit, a number of clock cycles elapsed during a change from the stop frequency to the start frequency by measuring the filtered output voltage, storing the number of clock cycles in the digital controller and controlling the phase preset circuit with the digital controller to supply the phase preset current.

### Claim 9 (depends on 8)

The method of claim 8 further comprising determining the phase preset current by multiplying a calibration current, supplied by the phase preset circuit to the filter, by the number of clock cycles, multiplied by a clock period, and divided by a duration of the chirp phase.

### Claim 10 (depends on 7)

The method of claim 7 wherein filtering the charge pump voltage comprises filtering with a low pass filter comprising a plurality of filter stages.

### Claim 11 (depends on 10)

The method of claim 10 further comprising distributing the phase preset current to each of the plurality of filter stages.

### Claim 12 (depends on 7)

The method of claim 7 further comprising limiting the bandwidth of the PLL to minimize a phase noise.

### Claim 13

A method for presetting a phase of a fast chirp Phase Locked Loop, PLL, comprising:
generating a Frequency Modulated Continuous Waveform, FMCW, with the PLL, the PLL including a low pass filter configured to generate a filtered output voltage by filtering a charge pump voltage of a charge pump, the charge pump responsive to a difference between a divided FMCW and a reference frequency waveform, the FMCW including a chirp phase and a return phase, the chirp phase including a first linear change of the FMCW from a start frequency to a stop frequency, and the return phase including a second linear change of the FMCW from the stop frequency to the start frequency; and
supplying a phase preset current to the low pass filter during a start frequency time preceding the chirp phase, wherein determining the phase preset current comprises:
measuring a start voltage from the filtered output voltage while an FMCW frequency is equal to the start frequency,
setting the FMCW frequency to the stop frequency, wherein the filtered output voltage equals a stop voltage,
disabling the charge pump, supplying a calibration current to the low pass filter, and counting a number of clock cycles elapsed during a change from the stop voltage to the start voltage, wherein each clock cycle has a clock period,
setting the phase preset current equal to the calibration current multiplied by the number of clock cycles, multiplied by the clock period, and divided by a duration of the chirp phase, and
enabling the charge pump, and supplying the phase preset current during a subsequent start frequency time.

### Claim 14 (depends on 13)

The method of claim 13 further comprising supplying the calibration current to the low pass filter during a startup phase, and supplying the phase preset current to the low pass filter during the start frequency time.

### Claim 15 (depends on 13)

The method of claim 13 wherein without the phase preset current, the PLL has a reduction in a usable chirp phase.

### Claim 16 (depends on 13)

The method of claim 13, wherein filtering the charge pump voltage comprises filtering with the low pass filter comprising a plurality of filter stages.

### Claim 17 (depends on 16)

The method of claim 16, further comprising distributing the phase preset current to each of the plurality of filter stages.

### Claim 18 (depends on 13)

The method of claim 13, wherein the divided FMCW is generated by a frequency divider.

### Claim 19 (depends on 18)

The method of claim 18, further comprising modifying a division ratio of the frequency divider to generate the chirp phase.

### Claim 20 (depends on 19)

The method of claim 19, wherein modifying the division ratio of the frequency divider further comprises modifying the division ratio of the frequency divider to generate the return phase.