Method for generating a bias current for biasing a differential pair of transistors and corresponding integrated circuit
AssigneeSTMicroelectronics (Rousset) SAS
InventorsVincent BINET, Yohan JOLY
Life of this patent
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Abstract
An operational amplifier integrated circuit includes a differential pair of transistors having a first input, a second input. A bias current generator applies a bias current to an output of the differential pair of transistors. A control loop generates a control voltage arising from a difference in potentials between the first input and the second input. An additional current that is added to the bias current is generated in response to the control voltage.
Claims31
A method for generating a bias current for biasing a differential pair of transistors which include a first input, a second input, a first intermediate output, a second intermediate output, the method comprising:
- generating a bias current for biasing the first intermediate output and the second intermediate output;
- generating a control voltage arising from a difference in potentials between the first input and the second input;
- and
- generating in response to the control voltage an additional current that is added to the bias current.
An integrated circuit, comprising:
- a differential pair of transistors including a first input, a second input, a first intermediate output, a second intermediate output,
- a bias current generator configured to generate a bias current for biasing the first intermediate output and the second intermediate output;
- a control loop configured to generate a control voltage arising from a difference in potentials between the first input and the second input, and to generate in response to the control voltage an additional current that is added to the bias current for biasing the first intermediate output and the second intermediate output.
An integrated circuit, comprising:
- a first differential pair of transistors including a first input, a second input, and a first common source bias node;
- a first current source configured to source a first bias current to the common source bias node;
- a transistor configured to generate a second bias current for application to the common source bias node;
- an amplifier circuit having a first input configured to receive a voltage at the first input and a second input configured to receive a voltage at the second input, the amplifier circuit configured to determine a difference between the voltage at the first and second inputs and output a control voltage for application to a control terminal of said transistor.
An integrated circuit, comprising:
- a first differential pair of transistors including a first input, a second input, and a first common source bias node;
- a first current source configured to source a first bias current to the common source bias node;
- a first transistor configured to generate a second bias current for application to the common source bias node;
- a second transistor configured to generate a third bias current for application to the common source bias node;
- an amplifier circuit having a first input configured to receive a voltage at the first input and a second input configured to receive a voltage at the second input, the amplifier circuit configured to determine a difference between the voltage at the first and second inputs and output a differential control voltage having a first control voltage for application to a control terminal of said first transistor and a second control voltage for application to a control terminal of said second transistor.
An integrated circuit, comprising:
- a first differential pair of transistors including a first input, a second input, and a first common source bias node;
- a first current source configured to source a first bias current to the common source bias node;
- and
- a transistor having a gate node connected to the first input and a drain node, wherein a second bias current is generated at the drain node for application to the common source bias node.
Dependencies are inferred from the claim text.