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US 2019/0371940 A1Published application
Method for fabricating transistor with thinned channel
AssigneeIntel Corporation
InventorsJustin K. Brask, Robert S. Chau, Suman Datta, Mark L. Doczy, Brian S. Doyle, Jack T. Kavalieros, Amlan Majumdar, Matthew V. Metz, Marko Radosavljevic
Life of this patent
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Abstract
A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.
Claims23
(canceled)
An apparatus comprising:
- a first portion of a semiconductor body, wherein the first portion is under a gate electrode, and wherein the first portion has a first width;
- and
- a second portion of the semiconductor body outside the gate electrode, wherein the second portion has a second width, wherein the second width is greater than the first width.
The apparatus of claim 2, wherein the second portion is closer to drain or source regions.
The apparatus of claim 3, wherein the source and drain comprise As or Ph.
A system comprising:
- a memory;
- a processor;
- and
- a network interface coupled to the processor via a bus, wherein the processor is at least one of:
- a central processing unit (CPU);
- a graphics processor;
- a digital signal processor;
- or a crypto processor, and wherein the memory comprises at least one of a volatile memory or non-volatile memory, wherein the processor includes:
- a first portion of a semiconductor body, wherein the first portion is under a gate electrode, and wherein the first portion has a first width;
- and
- a second portion of the semiconductor body outside the gate electrode, wherein the second portion has a second width, wherein the second width is greater than the first width.
8 more elements
A method comprising:
- forming a first portion of a semiconductor body, wherein the first portion is under a gate electrode, and wherein the first portion has a first width;
- and
- forming a second portion of the semiconductor body outside the gate electrode, wherein the second portion has a second width, wherein the second width is greater than the first width.
Dependencies are inferred from the claim text.