# US 2019/0356874 A1 · Sample-and-hold circuit with feedback and noise integration > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0356874 A1 - Document ID: US20190356874A1 - Status: Published application - Kind: A1 - Application number: 16/058,559 - Filed: 2018-08-08 - Published: 2019-11-21 - Earliest claimed: 2018-05-17 - Assignees: Sony Semiconductor Solutions Corporation - Applicants: Sony Semiconductor Solutions Corporation - Inventors: Noam Eshel; Golan Zeituni - Web page: https://patentgrep.com/patent/US20190356874A1 ## CPC - H04N 25/616: involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling - G11C 27/026: {associated with an amplifier (G11C27/028 takes precedence)} - H04N 25/78: Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters - H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A sample-and-hold circuit comprises a sampling capacitor; an amplifier transistor; and a noise reduction circuit including an integration capacitor and a feedback capacitor, the noise reduction circuit being configured to reduce noise via a four-phase operation including: an auto-zero phase in which the feedback capacitor is discharged, a feedback phase in which a gate voltage of the amplifier transistor is partially compensated through the feedback capacitor, an integration phase in which the integration capacitor is charged, and a feedforward phase in which the gate voltage of the amplifier transistor is fully compensated by a voltage on the integration capacitor through the feedback capacitor. ## Claims ### Claim 1 A sample-and-hold circuit, comprising: a sampling capacitor; an amplifier transistor; and a noise reduction circuit including an integration capacitor and a feedback capacitor, the noise reduction circuit being configured to reduce noise via a four-phase operation including: an auto-zero phase in which the feedback capacitor is discharged, a feedback phase in which a gate voltage of the amplifier transistor is partially compensated through the feedback capacitor, an integration phase in which the integration capacitor is charged, and a feedforward phase in which the gate voltage of the amplifier transistor is fully compensated by a voltage on the integration capacitor through the feedback capacitor. ### Claim 2 (depends on 1) The sample-and-hold circuit according to claim 1, further comprising a calibration circuit configured to adjust a transconductance of the amplifier transistor. ### Claim 3 (depends on 2) The sample-and-hold circuit according to claim 2, wherein the calibration circuit is configured to receive a first input signal from the sample-and-hold circuit, to receive a second input signal from a reference circuit, and integrate an error between the first input signal and the second input signal. ### Claim 4 (depends on 3) The sample-and-hold circuit according to claim 3, wherein the reference circuit is a reference sample-and-hold circuit having a similar configuration to the sample-and-hold circuit and further having a pulse input capacitor. ### Claim 5 (depends on 3) The sample-and-hold circuit according to claim 3, wherein the reference circuit is a reference sample-and-hold circuit to which an artificial error has been injected. ### Claim 6 (depends on 1) The sample-and-hold circuit according to claim 1, wherein the noise reduction circuit further includes a plurality of loop transistors. ### Claim 7 A method of reducing a noise in a sample-and-hold circuit including a sampling capacitor, and amplifier transistor, and a noise reduction circuit, the method comprising: discharging a feedback capacitor of the noise reduction circuit; partially compensating a gate voltage of the amplifier transistor through the feedback capacitor; charging the integration capacitor; and fully compensating the gate voltage of the amplifier transistor by a voltage on the integration capacitor through the feedback capacitor. ### Claim 8 (depends on 7) The method according to claim 7, further comprising adjusting a transconductance of the amplifier transistor by a calibration circuit of the sample-and-hold circuit. ### Claim 9 (depends on 8) The method according to claim 8, further comprising: receiving, by the calibration circuit, a first input signal from the sample-and-hold circuit; receiving, by the calibration circuit, a second input signal from a reference circuit; and integrating an error between the first input signal and the second input signal. ### Claim 10 (depends on 9) The method according to claim 9, wherein the reference circuit is a reference sample-and-hold circuit having a similar configuration to the sample-and-hold circuit and further having a pulse input capacitor. ### Claim 11 (depends on 9) The method according to claim 9, wherein the reference circuit is a reference sample-and-hold circuit to which an artificial error has been injected. ### Claim 12 (depends on 9) The method according to claim 9, wherein the noise reduction circuit further includes a plurality of loop transistors. ### Claim 13 An image sensor, comprising: a plurality of pixel circuits arranged in an array; a sample-and-hold circuit; and an analog-to-digital converter configured to receive an output from the sample-and-hold circuit, wherein the sample-and-hold circuit includes a sampling capacitor, an amplifier transistor, and a noise reduction circuit having an integration capacitor and a feedback capacitor, the noise reduction circuit being configured to reduce noise via a four-phase operation including: an auto-zero phase in which the feedback capacitor is discharged, a feedback phase in which a gate voltage of the amplifier transistor is partially compensated through the feedback capacitor, an integration phase in which the integration capacitor is charged, and a feedforward phase in which the gate voltage of the amplifier transistor is fully compensated by a voltage on the integration capacitor through the feedback capacitor. ### Claim 14 (depends on 13) The image sensor according to claim 13, wherein the sample-and-hold circuit further includes a calibration circuit configured to adjust a transconductance of the amplifier transistor. ### Claim 15 (depends on 14) The image sensor according to claim 14, wherein the calibration circuit is configured to receive a first input signal from the sample-and-hold circuit, to receive a second input signal from a reference circuit, and integrate an error between the first input signal and the second input signal. ### Claim 16 (depends on 15) The image sensor according to claim 15, wherein the reference circuit is a reference sample-and-hold circuit having a similar configuration to the sample-and-hold circuit and further having a pulse input capacitor. ### Claim 17 (depends on 15) The image sensor according to claim 15, wherein the reference circuit is a reference sample-and-hold circuit to which an artificial error has been injected. ### Claim 18 (depends on 13) The image sensor according to claim 13, wherein the noise reduction circuit further includes a plurality of loop transistors. ### Claim 19 (depends on 13) The image sensor according to claim 13, wherein the sample-and-hold circuit is configured to sample a signal from a respective pixel circuit of the plurality of pixel circuits, the signal corresponding to an amount of received light by the respective pixel circuit. ### Claim 20 (depends on 13) The image sensor according to claim 13, wherein the analog-to-digital converter is configured to receive an analog signal from the sample-and-hold circuit and convert the analog signal to a digital signal.