# US 2019/0356519 A1 · Low power physical layer driver topologies > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0356519 A1 - Document ID: US20190356519A1 - Status: Published application - Kind: A1 - Application number: 16/526,332 - Filed: 2019-07-30 - Published: 2019-11-21 - Earliest claimed: 2015-06-22 - Assignees: QUALCOMM Incorporated - Applicants: QUALCOMM Incorporated - Inventors: Shih-Wei CHOU; Chulkyu LEE; Dhaval SEJPAL - Web page: https://patentgrep.com/patent/US20190356519A1 ## CPC - H04L 25/493: by transition coding, i.e. the time-position or direction of a transition being encoded before transmission - G06F 13/4072: {Drivers or receivers (G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002)} - H04B 1/04: Circuits - H04B 3/52: Systems for transmission between fixed stations via waveguides - H04L 25/02: Details {; arrangements for supplying electrical power along data transmission lines (systems for transmitting signals via power distribution lines H04B3/54)} - H04L 25/0272: {Arrangements for coupling to multiple lines, e.g. for differential transmission} - H04L 25/0276: {Arrangements for coupling common mode signals} - H04L 25/028: {Arrangements specific to the transmitter end} - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H04B: TRANSMISSION ## Abstract System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within electronic equipment. Transmission lines are selectively terminated in an N-phase polarity encoded transmitter when the transmission lines would otherwise be undriven. Data is mapped to a sequence of symbols to be transmitted on a plurality of wires. The sequence of symbols is encoded in three signals. A first terminal of a plurality of terminals may be driven such that transistors are activated to couple the first terminal to first and second voltage levels. The first terminal may further be driven such that a dedicated transistor is activated to couple the first terminal to an intermediate voltage level. ## Claims ### Claim 1 A transmitter, comprising: a plurality of terminals; and a line driver configured to transmit a signal via a terminal of the plurality of terminals, the signal being in one of three phases, wherein the line driver includes a first transistor, a second transistor, and a third transistor, wherein a source of the first transistor, a source of the third transistor, a first end of a resistor, and a drain of the second transistor are coupled to each other, and wherein a second end of the resistor is coupled to the terminal, and wherein the line driver is configured to: drive the terminal towards a first voltage level by turning on the first transistor when the signal is in a first phase, drive the terminal towards a second voltage level by turning on the second transistor when the signal is in a second phase, and drive the terminal towards a third voltage level by turning on the third transistor when the signal is in a third phase. ### Claim 2 (depends on 1) The transmitter of claim 1, further including a processing circuit coupled to the line driver, the processing circuit configured to: map data to a sequence of symbols to be transmitted on a plurality of wires via the plurality of terminals; encode the sequence of symbols in three signals, wherein each of the three signals is in one of three phases for each symbol to be transmitted, and wherein the three signals are in different phases from one another during transmission of each symbol; and obtain the signal to be transmitted via the terminal of the plurality of terminals, wherein the signal is one of the three signals. ### Claim 3 (depends on 1) The transmitter of claim 1, wherein: the first transistor is sourced by a first voltage supply; and the third transistor is sourced by a second voltage supply, wherein the first voltage supply is regulated by a first voltage regulator that is different from a second voltage regulator that regulates the second voltage supply. ### Claim 4 (depends on 3) The transmitter of claim 3, wherein a first end of a second resistor is coupled to the first voltage supply, and a second end of the second resistor is coupled to a drain of the first transistor. ### Claim 5 (depends on 4) The transmitter of claim 4, wherein a first end of a third resistor is coupled to a source of the second transistor, and a second end of the third resistor is coupled to a ground node. ### Claim 6 (depends on 5) The transmitter of claim 5, wherein a first end of a fourth resistor is coupled to the second voltage supply, and a second end of the fourth resistor is coupled to a drain of the third transistor. ### Claim 7 (depends on 1) The transmitter of claim 1, wherein when one of the first transistor, the second transistor, and the third transistor is turned on, a remaining two of the first transistor, the second transistor, and the third transistor are turned off. ### Claim 8 A method of data transfer, comprising: obtaining a signal to be transmitted via a terminal of a plurality of terminals, wherein the signal is in one of three phases; driving the terminal towards a first voltage level by turning on a first transistor when the signal is in a first phase; driving the terminal towards a second voltage level by turning on a second transistor when the signal is in a second phase; and driving the terminal towards a third voltage level by turning on a third transistor when the signal is in a third phase, wherein a source of the first transistor, a source of the third transistor, a first end of a resistor, and a drain of the second transistor are coupled to each other, and wherein a second end of the resistor is coupled to the terminal. ### Claim 9 (depends on 8) The method of claim 8, further including: mapping data to a sequence of symbols to be transmitted on a plurality of wires via the plurality of terminals; and encoding the sequence of symbols in three signals, wherein each of the three signals is in one of three phases for each symbol to be transmitted, and wherein the three signals are in different phases from one another during transmission of each symbol, wherein the signal to be transmitted via the terminal of the plurality of terminals is one of the three signals. ### Claim 10 (depends on 8) The method of claim 8, wherein: the first transistor is sourced by a first voltage supply; and the third transistor is sourced by a second voltage supply, wherein the first voltage supply is regulated by a first voltage regulator that is different from a second voltage regulator that regulates the second voltage supply. ### Claim 11 (depends on 10) The method of claim 10, wherein a first end of a second resistor is coupled to the first voltage supply, and a second end of the second resistor is coupled to a drain of the first transistor. ### Claim 12 (depends on 11) The method of claim 11, wherein a first end of a third resistor is coupled to a source of the second transistor, and a second end of the third resistor is coupled to a ground node. ### Claim 13 (depends on 12) The method of claim 12, wherein a first end of a fourth resistor is coupled to the second voltage supply, and a second end of the fourth resistor is coupled to a drain of the third transistor. ### Claim 14 (depends on 8) The method of claim 8, wherein the third voltage level is within a voltage range bounded by the first voltage level and the second voltage level. ### Claim 15 A processor-readable storage medium having one or more instructions which, when executed by at least one processing circuit, cause the at least one processing circuit to: obtain a signal to be transmitted via a terminal of a plurality of terminals, wherein the signal is in one of three phases; drive the terminal towards a first voltage level by turning on a first transistor when the signal is in a first phase; drive the terminal towards a second voltage level by turning on a second transistor when the signal is in a second phase; and drive the terminal towards a third voltage level by turning on a third transistor when the signal is in a third phase, wherein a source of the first transistor, a source of the third transistor, a first end of a resistor, and a drain of the second transistor are coupled to each other, and wherein a second end of the resistor is coupled to the terminal. ### Claim 16 (depends on 15) The processor-readable storage medium of claim 15, wherein the one or more instructions further cause the at least one processing circuit to: map data to a sequence of symbols to be transmitted on a plurality of wires via the plurality of terminals; and encode the sequence of symbols in three signals, wherein each of the three signals is in one of three phases for each symbol to be transmitted, and wherein the three signals are in different phases from one another during transmission of each symbol, wherein the signal to be transmitted via the terminal of the plurality of terminals is one of the three signals. ### Claim 17 (depends on 15) The processor-readable storage medium of claim 15, wherein: the first transistor is sourced by a first voltage supply; and the third transistor is sourced by a second voltage supply, wherein the first voltage supply is regulated by a first voltage regulator that is different from a second voltage regulator that regulates the second voltage supply. ### Claim 18 (depends on 17) The processor-readable storage medium of claim 17, wherein a first end of a second resistor is coupled to the first voltage supply, and a second end of the second resistor is coupled to a drain of the first transistor. ### Claim 19 (depends on 18) The processor-readable storage medium of claim 18, wherein a first end of a third resistor is coupled to a source of the second transistor, and a second end of the third resistor is coupled to a ground node. ### Claim 20 (depends on 19) The processor-readable storage medium of claim 19, wherein a first end of a fourth resistor is coupled to the second voltage supply, and a second end of the fourth resistor is coupled to a drain of the third transistor.