# US 2019/0356468 A1 · Automotive nonce-misuse-resistant authenticated encryption

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- Number: US 2019/0356468 A1
- Document ID: US20190356468A1
- Status: Published application
- Kind: A1
- Application number: 15/983,594
- Filed: 2018-05-18
- Published: 2019-11-21
- Earliest claimed: 2018-05-18
- Assignees: Infineon Technologies AG
- Applicants: Infineon Technologies AG
- Inventors: Alexander ZEH; Patrick KRESMER
- Web page: https://patentgrep.com/patent/US20190356468A1

## CPC

- H04L 9/0631: {Substitution permutation network [SPN], i.e. cipher composed of a number of stages or rounds each involving linear and nonlinear transformations, e.g. AES algorithms}
- H04L 9/0637: {Modes of operation, e.g. cipher block chaining [CBC], electronic codebook [ECB] or Galois/counter mode [GCM]}
- H04L 9/0861: {Generation of secret information including derivation or calculation of cryptographic keys or passwords}
- H04L 2209/125: Parallelization or pipelining, e.g. for accelerating processing of cryptographic operations
- H04L 2209/46: Secure multiparty computation, e.g. millionaire problem
- H04L 2209/84: Vehicles
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

A system may include a plurality of matching block cipher devices, and a hardware state machine communicatively coupled to each of the plurality of matching block cipher devices. Each of the plurality of matching block cipher devices can be independently invoked by the hardware state machine such that the hardware state machine causes two or more of the plurality of matching block cipher devices to selectively perform a block-cipher-based symmetric cryptographic operation in a redundant mode or a parallel mode. The block-cipher-based symmetric cryptographic operation may be associated with securing a communication channel of an automotive system.

## Claims

### Claim 1

A system, comprising:
a plurality of matching block cipher devices; and
a hardware state machine communicatively coupled to each of the plurality of matching block cipher devices,
wherein each of the plurality of matching block cipher devices can be independently invoked by the hardware state machine such that the hardware state machine causes two or more of the plurality of matching block cipher devices to selectively perform a block-cipher-based symmetric cryptographic operation in a redundant mode or a parallel mode,
wherein the block-cipher-based symmetric cryptographic operation is associated with securing a communication channel of an automotive system.

### Claim 2 (depends on 1)

The system of claim 1, wherein the plurality of matching block cipher devices is a plurality of Advanced Encryption Standard (AES) accelerators.

### Claim 3 (depends on 1)

The system of claim 1, wherein the block-cipher-based symmetric cryptographic operation is associated with an authenticated encryption with additional data (AEAD) scheme that provides nonce-misuse-resistance,
wherein the AEAD scheme requires a single type of cryptographic primitive.

### Claim 4 (depends on 3)

The system of claim 3, wherein the two or more block cipher devices form a pseudo random function (PRF) and act as a counter (CTR) mode accelerator,
wherein the PRF is based on cipher block chaining (CBC) and uses a first secret key and a second secret key, and
wherein the CTR mode accelerator uses a third secret key.

### Claim 5 (depends on 1)

The system of claim 1, wherein the redundant mode is a concurrent redundant mode or a time-offset redundant mode.

### Claim 6

A method, comprising:
receiving, by a hardware state machine, a command associated with a block-cipher-based symmetric cryptographic operation,
wherein the block-cipher-based symmetric cryptographic operation is associated with securing a communication channel of an automotive system;
causing, by the hardware state machine and based on the command, one or more block cipher devices to perform the block-cipher-based symmetric cryptographic operation,
wherein the one or more block cipher devices are included in a plurality of matching block cipher devices communicatively coupled to the hardware state machine,
wherein the one or more block cipher devices form a pseudo random function (PRF) and act as a counter (CTR) mode,
wherein the pseudo random function (PRF) is based on cipher block chaining (CBC) and uses a first secret key and a second secret key, and
wherein the counter (CTR) mode uses a third secret key;
receiving, by the hardware state machine and from the one or more block cipher devices, one or more intermediate results associated with the block-cipher-based symmetric cryptographic operation; and
providing, by the hardware state machine, a final result associated with the block-cipher-based symmetric cryptographic operation.

### Claim 7 (depends on 6)

The method of claim 6, wherein the plurality of matching block cipher devices is a plurality of Advanced Encryption Standard (AES) accelerators.

### Claim 8 (depends on 6)

The method of claim 6, wherein the one or more block cipher devices includes at least two block cipher devices,
wherein a first block cipher device, of the at least two block cipher devices, forms the PRF, and
wherein a second block cipher device, of the at least two block cipher devices, acts as the CTR mode accelerator.

### Claim 9 (depends on 6)

The method of claim 6, wherein the block-cipher-based symmetric cryptographic operation is associated with an authenticated encryption with additional data (AEAD) scheme that provides nonce-misuse-resistance,
wherein the AEAD scheme requires a single type of cryptographic primitive.

### Claim 10 (depends on 6)

The method of claim 6, wherein the one or more block cipher devices includes at least two block cipher devices operating in a parallel mode.

### Claim 11 (depends on 6)

The method of claim 6, wherein the one or more block cipher devices includes at least two block cipher devices operating in a redundant mode.

### Claim 12 (depends on 6)

The method of claim 6, further comprising:
causing at least one of the plurality of matching block cipher devices to derive the first secret key, the second secret key, or the third secret key based on a master secret key.

### Claim 13 (depends on 6)

The method of claim 6, wherein the final result is provided to a host processor of an electronic control unit (ECU) associated with the automotive system.

### Claim 14

A system, comprising:
a plurality of block cipher devices,
wherein each of the plurality of block cipher devices is associated with the same cryptographic primitive; and
a state machine, at least partially implemented in hardware and communicatively coupled to each of the plurality of block cipher devices, to:
receive a command associated with a cryptographic operation associated with securing a communication channel of an automotive system,
wherein the cryptographic operation is a block-cipher-based symmetric cryptographic operation,
cause, based on the command, two or more block cipher devices, of the plurality of block cipher devices, to perform the cryptographic operation,
wherein each of the one or more block cipher devices performs the cryptographic operation in a redundant mode or a parallel mode,
receive, from the one or more block cipher devices, an intermediate result associated with the cryptographic operation, and
provide, based on the intermediate result, a final result associated with the cryptographic operation.

### Claim 15 (depends on 14)

The system of claim 14, wherein the plurality of block cipher devices is a plurality of Advanced Encryption Standard (AES) accelerators.

### Claim 16 (depends on 14)

The system of claim 14, wherein the block-cipher-based symmetric cryptographic operation is associated with an authenticated encryption with additional data (AEAD) scheme that provides nonce-misuse-resistance.

### Claim 17 (depends on 14)

The system of claim 14, wherein the two or more block cipher devices form a pseudo random function (PRF) and act as a counter (CTR) mode accelerator,
wherein the PRF is based on cipher block chaining (CBC) and uses a first secret key and a second secret key, and
wherein the CTR mode accelerator uses a third secret key.

### Claim 18 (depends on 17)

The system of claim 17, wherein a first block cipher device, of the two or more block cipher devices, forms the PRF, and a second block cipher device, of the two or more block cipher devices, acts as the CTR mode accelerator.

### Claim 19 (depends on 14)

The system of claim 14, wherein the state machine is further to:
cause at least one of the plurality of block cipher devices to generate one or more secret keys based on a master secret key.

### Claim 20 (depends on 14)

The system of claim 14, wherein the final result is provided to a host processor of an Electronic Control Unit (ECU) associated with the automotive system.