# US 2019/0356414 A1 · Low density parity check encoder, and low density parity check encoding method using the same

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2019/0356414 A1
- Document ID: US20190356414A1
- Status: Published application
- Kind: A1
- Application number: 16/529,502
- Filed: 2019-08-01
- Published: 2019-11-21
- Earliest claimed: 2014-08-26
- Assignees: Electronics and Telecommunications Research Institute
- Applicants: Electronics and Telecommunications Research Institute
- Inventors: Sung-Ik PARK; Heung-Mook KIM; Sun-Hyoung KWON; Nam-Ho HUR
- Web page: https://patentgrep.com/patent/US20190356414A1

## CPC

- H04L 1/0042: {Encoding specially adapted to other signal generation operation, e.g. in order to reduce transmit distortions, jitter, or to improve signal shape (H04L1/0067 takes precedence)}
- H03M 13/036: {Heuristic code construction methods, i.e. code construction or code search based on using trial-and-error}
- H03M 13/1165: {QC-LDPC codes as defined for the digital video broadcasting [DVB] specifications, e.g. DVB-Satellite [DVB-S2]}
- H03M 13/1185: {wherein the parity-check matrix comprises a part with a double-diagonal}
- H03M 13/31: combining coding for error detection or correction and efficient use of the spectrum (without error detection or correction H03M5/14 {, H03M5/145})
- H03M 13/6502: {Reduction of hardware complexity or efficient processing}
- H04L 1/0057: {Block codes (H04L1/0061, H04L1/0064 take precedence)}
- H04L 1/0058: {Block-coded modulation}
- H04L 1/0071: {Use of interleaving (interleaving per se H03M13/27)}
- H03M 13/1102: {Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes}
- H03M 13/1148: {Structural properties of the code parity-check or generator matrix}
- H03M 13/116: {Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices}
- H03M 13/255: {with Low Density Parity Check [LDPC] codes}
- H03M 13/27: using interleaving techniques
- H03M 13/2921: {wherein error correction coding involves a diagonal direction}
- H04L 1/0041: {Arrangements at the transmitter end}
- H04L 27/2627: {Modulators}
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword. The second memory is initialized to 0. The processor generates the LDPC codeword by performing accumulation with respect to the second memory using information bits. The accumulation is performed at parity bit addresses that are updated using a sequence corresponding to a parity check matrix (PCM).

## Claims

### Claim 1

A low density parity check (LDPC) decoder, comprising:
a receiving unit configured to receive a signal corresponding to an LDPC codeword, the LDPC codeword generated by performing accumulation at parity bit addresses that are updated using a sequence corresponding to a parity check matrix (PCM); and
a decoding unit configured to perform decoding the received signal, the decoding corresponding to the parity check matrix.

### Claim 2 (depends on 1)

The LDPC decoder of claim 1, wherein the LDPC codeword comprises a systematic part corresponding to information bits, a first parity part corresponding to a dual diagonal matrix of the PCM, and a second parity part corresponding to an identity matrix of the PCM.

### Claim 3 (depends on 2)

The LDPC decoder of claim 2, wherein the parity bit addresses are updated based on results of comparing each of previous parity bit addresses specified in each row of the sequence with the size of the first parity part.

### Claim 4 (depends on 2)

The LDPC decoder of claim 2, wherein the parity bit addresses are updated in accordance with the following equation:
(x+m×Q1) mod M1 if x<M1
M1+{(x−M1+m×Q2) mod M2} if x≥M1
where x denotes the previous parity bit addresses, m is an information bit index, L is a circulant permutation matrix (CPM) size of the PCM, Q1 is M1/L, M1 is the size of the first parity part, Q2 is M2/L, and M2 is the size of the second parity part.

### Claim 5 (depends on 4)

The LDPC decoder of claim 4, wherein the accumulation is performed using memory having a size corresponding to a sum of a size of the first parity part and a size of the second parity part.

### Claim 6 (depends on 5)

The LDPC decoder of claim 5, wherein the accumulation is performed while the rows of the sequence are being repeatedly changed by the CPM size of the PCM.

### Claim 7

A low density parity check (LDPC) decoding method, comprising:
receiving a signal corresponding to an LDPC codeword, the LDPC codeword generated by performing accumulation at parity bit addresses that are updated using a sequence corresponding to a parity check matrix (PCM); and
decoding the received signal, the decoding corresponding to the parity check matrix,
wherein the LDPC codeword comprises a systematic part corresponding to information bits, a first parity part corresponding to a dual diagonal matrix of the PCM, and a second parity part corresponding to an identity matrix of the PCM.