# US 2019/0356341 A1 · Data processing method and device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0356341 A1 - Document ID: US20190356341A1 - Status: Published application - Kind: A1 - Application number: 16/531,956 - Filed: 2019-08-05 - Published: 2019-11-21 - Earliest claimed: 2017-02-06 - Assignees: Huawei Technologies Co., Ltd. - Applicants: Huawei Technologies Co., Ltd. - Inventors: Liang MA; Chen ZHENG; Xin ZENG; Yuejun WEI - Web page: https://patentgrep.com/patent/US20190356341A1 ## CPC - H03M 13/39: Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes - H04L 1/0013: {Rate matching, e.g. puncturing or repetition of code symbols} - H03M 13/1148: {Structural properties of the code parity-check or generator matrix} - H03M 13/116: {Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices} - H03M 13/27: using interleaving techniques - H03M 13/271: {Row-column interleaver with permutations, e.g. block interleaving with inter-row, inter-column, intra-row or intra-column permutations} - H03M 13/6362: {by puncturing} - H04L 1/0057: {Block codes (H04L1/0061, H04L1/0064 take precedence)} - H04L 1/0071: {Use of interleaving (interleaving per se H03M13/27)} - H04L 1/18: Automatic repetition systems, e.g. Van Duuren systems - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract Embodiments of this application disclose a data processing method and a data processing device. The method includes: obtaining a first to-be-processed bit sequence, where the first to-be-processed bit sequence is a transport block or a code block generated by performing code block segmentation on a transport block; encoding the first to-be-processed bit sequence to obtain a first encoded bit sequence; storing all or at least some bits of the first encoded bit sequence into a circular buffer; and outputing a first output bit sequence from the bits stored in the circular buffer. According to the method and the device that are provided in this application, rate matching can be implemented for a sequence generated through LDPC encoding. ## Claims ### Claim 1 A data processing method, comprising: obtaining a first to-be-processed bit sequence, wherein the first to-be-processed bit sequence is a transport block or a code block generated by performing code block segmentation on a transport block; encoding the first to-be-processed bit sequence to obtain a first encoded bit sequence; and outputting a first output bit sequence from bits stored in a circular buffer, wherein the circular buffer is configured to store all or some bits of the first encoded bit sequence, or the circular buffer is configured to store all or some bits of a first reordered bit sequence that is obtained by performing bit reordering on the first encoded bit sequence. ### Claim 2 (depends on 1) The method according to claim 1, wherein the first reordered bit sequence is obtained by changing a position of a first subsequence in the first encoded bit sequence, and a length of the first subsequence is a positive integer multiple of an lifting factor; or the first reordered bit sequence is obtained by deleting a second subsequence in the first encoded bit sequence, and a length of the second subsequence is a positive integer multiple of an lifting factor. ### Claim 3 (depends on 1) The method according to claim 1, wherein the obtaining a first to-be-processed bit sequence comprises: obtaining the transport block; and generating, based on the transport block, N bit sequences that comprise the first to-be-processed bit sequence, wherein N is an integer greater than 0. ### Claim 4 (depends on 1) The method according to claim 1, further comprising: interleaving the first output bit sequence. ### Claim 5 (depends on 1) The method according to claim 1, further comprising: generating a vector sequence based on the first output bit sequence, wherein the vector sequence comprises Q vectors of the first output bit sequence, each vector of the first output bit sequence comprises at least one bit of the first output bit sequence, and Q is a positive integer; and interleaving the vector sequence. ### Claim 6 (depends on 5) The method according to claim 5, wherein the vector sequence further comprises vectors generated based on a second output bit sequence, and each vector of the second output bit sequence comprises at least one bit of the second output bit sequence. ### Claim 7 (depends on 5) The method according to claim 5, wherein the interleaving the vector sequence comprises: interleaving the vectors comprised in the vector sequence. ### Claim 8 (depends on 5) The method according to claim 5, wherein the interleaving the vector sequence comprises: performing intra-vector-subsequence interleaving on each vector subsequence comprised in the vector sequence to obtain M interleaved subsequences, wherein the vector sequence comprises M vector subsequences, and a quantity of vectors comprised in each vector subsequence is a positive integer multiple of a quantity of vectors comprised in a time domain symbol on a channel used to transmit the transport block within one transmission time interval. ### Claim 9 A data processing device, comprising: a processor; and a non-transitory computer-readable storage medium coupled to the processor and storing programming instructions for execution by the processor, the programming instructions instruct the processor to: obtain a first to-be-processed bit sequence, wherein the first to-be-processed bit sequence is a transport block or a code block generated by performing code block segmentation on a transport block; encode the first to-be-processed bit sequence to obtain a first encoded bit sequence; and output a first output bit sequence from a circular buffer, wherein the circular buffer is configured to store all or some bits of the first encoded bit sequence, or the circular buffer is configured to store all or some bits of a first reordered bit sequence that is obtained by performing bit reordering on the first encoded bit sequence. ### Claim 10 (depends on 9) The data processing device according to claim 9, wherein the first reordered bit sequence is obtained by changing a position of a first subsequence in the first encoded bit sequence, and a length of the first subsequence is a positive integer multiple of an lifting factor; or the first reordered bit sequence is obtained by deleting a second subsequence in the first encoded bit sequence, and a length of the second subsequence is a positive integer multiple of an lifting factor. ### Claim 11 (depends on 9) The data processing device according to claim 9, wherein the programming instructions instruct the processor to: obtain the transport block; and generate, based on the transport block, N bit sequences that comprise the first to-be-processed bit sequence, wherein N is an integer greater than 0. ### Claim 12 (depends on 9) The data processing device according to claim 9, the programming instructions instruct the processor to: interleave the first output bit sequence. ### Claim 13 (depends on 9) The data processing device according to claim 9, the programming instructions instruct the processor to: generate a vector sequence based on the first output bit sequence, wherein the vector sequence comprises Q vectors of the first output bit sequence, each vector of the first output bit sequence comprises at least one bit of the first output bit sequence, and Q is a positive integer; and interleave the vector sequence. ### Claim 14 (depends on 13) The data processing device according to claim 13, wherein the vector sequence further comprises vectors generated based on a second output bit sequence, and each vector of the second output bit sequence comprises at least one bit of the second output bit sequence. ### Claim 15 (depends on 13) The data processing device according to claim 13, wherein the programming instructions instruct the processor to: interleave the vectors comprised in the vector sequence. ### Claim 16 (depends on 13) The data processing device according to claim 13, wherein the programming instructions instruct the processor to: perform intra-vector-subsequence interleaving on each vector subsequence comprised in the vector sequence to obtain M interleaved subsequences, wherein the vector sequence comprises M vector subsequences, and a quantity of vectors comprised in each vector subsequence is a positive integer multiple of a quantity of vectors comprised in a time domain symbol on a channel used to transmit the transport block within one transmission time interval. ### Claim 17 A non-transitory computer readable medium comprising computer program codes stored thereon, executable by one or more digital processors for providing data procession, the computer program codes including: instructions for obtaining a first to-be-processed bit sequence, wherein the first to-be-processed bit sequence is a transport block or a code block generated by performing code block segmentation on a transport block; instructions for encoding the first to-be-processed bit sequence to obtain a first encoded bit sequence; and instructions for outputting a first output bit sequence from bits stored in a circular buffer, wherein the circular buffer is configured to store all or some bits of the first encoded bit sequence, or the circular buffer is configured to store all or some bits of a first reordered bit sequence that is obtained by performing bit reordering on the first encoded bit sequence. ### Claim 18 (depends on 17) The non-transitory computer readable medium according to claim 17, wherein the first reordered bit sequence is obtained by changing a position of a first subsequence in the first encoded bit sequence, and a length of the first subsequence is a positive integer multiple of an lifting factor; or the first reordered bit sequence is obtained by deleting a second subsequence in the first encoded bit sequence, and a length of the second subsequence is a positive integer multiple of an lifting factor. ### Claim 19 (depends on 17) The non-transitory computer readable medium according to claim 17, wherein the computer program codes including: instructions for interleaving the first output bit sequence. ### Claim 20 (depends on 17) The non-transitory computer readable medium according to claim 17. wherein the computer program codes including: instructions for generating a vector sequence based on the first output bit sequence, wherein the vector sequence comprises Q vectors of the first output bit sequence, each vector of the first output bit sequence comprises at least one bit of the first output bit sequence, and Q is a positive integer; and instructions for interleaving the vector sequence.