# US 2019/0356325 A1 · Comparator offset voltage self-correction circuit

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- Number: US 2019/0356325 A1
- Document ID: US20190356325A1
- Status: Published application
- Kind: A1
- Application number: 16/476,106
- Filed: 2016-06-27
- Published: 2019-11-21
- Earliest claimed: 2016-06-20
- Assignees: China Electronic Technology Corporation, 24Th Research Institute
- Applicants: China Electronic Technology Corporation, 24Th Research Institute
- Inventors: RONG-BIN HU; YONG-LU WANG; GANG-YI HU; HE-QUAN JIANG; ZHENG-PING ZHANG; GUANG-BING CHEN; DONG-BING FU; YU-XIN WANG; LEI ZHANG; RONG-KE YE; CAN ZHU; YU-HAN GAO
- Web page: https://patentgrep.com/patent/US20190356325A1

## CPC

- H03F 3/45183: {Long tailed pairs (H03F3/4521, H03F3/45237 take precedence)}
- H03M 1/0607: {Offset or drift compensation (removal of offset already present on the analogue input signal H03M1/1295)}
- H03F 3/45766: {by using balancing means}
- H03K 5/2481: {with at least one differential stage}
- H03K 5/249: {using clock signals}
- H03M 1/1023: {Offset correction (H03M1/1019 takes precedence; removal of offset already present on the analogue input signal H03M1/1295)}
- H03M 1/365: {the voltage divider being a single resistor string}
- H03F: AMPLIFIERS
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A comparator offset voltage self-correction circuit is disclosed. A comparator offset voltage which is caused by the semiconductor process parameter randomness also has randomness. Due to the randomness of the comparator offset voltage, a reference voltage of a parallel comparator in a parallel-conversion-type analog-to-digital converter is uncertain. If the comparator offset voltage is large, the parallel-conversion-type analog-to-digital converter may even have a functional error. The comparator offset voltage self-correction circuit provided in the present invention can correct a random offset voltage of a comparator to meet requirements. Therefore, by means of the circuit and a method provided in the present invention, adverse influence of the random offset of the comparator on the function and the performance of the parallel-conversion-type analog-to-digital converter is eliminated, thereby greatly improving the speed and the performance of the analog-to-digital converter, in particular the parallel-conversion-type analog-to-digital converter.

## Claims

### Claim 1

A comparator offset voltage self-correction circuit, comprising: a comparator, an offset digital adjustment circuit, a successive approximation register, a multiplexer, an enable port, a clock port, a reference voltage input port Vr, an analog signal input port Vin, a correction voltage input port Vcal and an output port, wherein the reference voltage input port Vr is configured to receive a reference voltage, the correction voltage input port Vcal is configured to receive a correction voltage, and the correction voltage is generated by a high-accuracy DAC on the same chip or by a test instrument, and is connected to a chip through a chip pin; the analog signal input port Vin is configured to receive an analog signal; the output port is configured to output a comparison result; the multiplexer is connected to the analog signal input port Vin during normal operation, and is connected to the correction voltage input port Vcal during correction; the reference voltage input port Vr is connected to a port A of the offset digital adjustment circuit, a port B of the offset digital adjustment circuit is connected to an inverting input end VM of the comparator, and a non-inverting input end of the comparator is connected to an output port of the multiplexer; a first input port of the multiplexer is connected to the correction voltage input port Vcal, and a second input port of the multiplexer is connected to the analog signal input port Vin; an output end of the comparator is connected to a data input end Din of the successive approximation register, an enable end of the successive approximation register is connected to the enable port, and a clock end of the successive approximation register is connected to the clock port; data output ports D0, D1, D2, D3, D4, D5, D6 and D7 of the successive approximation register output data signals D0, D1, D2, D3, D4, D5, D6 and D7 which control data ports D0, D1, D2, D3, D4, D5, D6 and D7 of the offset digital adjustment circuit, respectively; a voltage VAB between the port B and the port A of the offset digital adjustment circuit is
V
AB
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wherein Vs is a designed voltage value.

### Claim 2 (depends on 1)

The comparator offset voltage self-correction circuit of claim 1, wherein a relationship between the VAB between the port B and the port A of the offset digital adjustment circuit and the data ports D0, D1, D2, D3, D4, D5, D6 and D7 of the offset digital adjustment circuit is a weighted summation relationship with an offset of Vs/2, the lowest weight bit being D0, the highest weight bit being D7, and the minimum change step size is Vs/27.

### Claim 3 (depends on 1)

The comparator offset voltage self-correction circuit of claim 1, wherein an electric potential of the inverting input end VM of the comparator is the sum of a voltage of the reference voltage input port Vr and a voltage drop of the ports of the offset digital adjustment circuit.

### Claim 4 (depends on 1)

The comparator offset voltage self-correction circuit of claim 1, wherein a correction process of the comparator offset voltage self-correction circuit is as follows:
first, the enable signal is at a low level, the successive approximation register is reset, the digital signals D7, D6, D5, D4, D3, D2, D1 and D0 adopt a default value 10,000,000, a port voltage drop of the offset digital adjustment circuit is 0, and an electric potential of the inverting input end VM of the comparator is the sum of a reference voltage and a comparator offset voltage;
second, the level of the enable signal jumps from a low level to a high level to start a correction process, the first input port of the multiplexer is connected so that a correction voltage Vcal is selected;
third, a rising edge of the first clock signal arrives, the successive approximation register keeps the default value 10,000,000 of the digital signals D7, D6, D5, D4, D3, D2, D1 and D0 unchanged, and the electric potential of the inverting input end VM of the comparator is unchanged;
fourth, the comparator compares voltage signals of the non-inverting input end and the inverting input end of the comparator, and feeds a comparison result back to the data input end Din of the successive approximation register;
if VM is lower than Vcal, when the rising edge of the second clock signal arrives, the successive approximation register keeps D7 at 1, while setting D6 as 1, and increasing VM by Vs/4; or
if VM is higher than Vcal, when the rising edge of the second clock signal arrives, the successive approximation register sets D7 as 0, while setting D6 as 1, and decreasing VM by Vs/4;
fifth, the comparator compares VM with Vcal again, and feeds a comparison result back to the data input end Din of the successive approximation register;
if VM is lower than Vcal, when the rising edge of the third clock signal arrives, the successive approximation register keeps D6 at 1, while setting D5 as 1, and increasing VM by Vs/8; or
if VM is higher than Vcal, when the rising edge of the third clock signal arrives, the successive approximation register sets D6 as 0, while setting D5 as 1, and decreasing VM by Vs/8;
sixth, the comparator compares VM with Vcal again, and feeds a comparison result back to the data input end Din of the successive approximation register;
if VM is lower than Vcal, when the rising edge of the fourth clock signal arrives, the successive approximation register keeps D5 at 1, while setting D4 as 1, and increasing VM by Vs/16; or
if VM is higher than Vcal, when the rising edge of the fourth clock signal arrives, the successive approximation register sets D5 as 0, while setting D4 as 1, and decreasing VM by Vs/16;
similarly, when the rising edge of the fifth clock signal arrives, the successive approximation register determines D4; when the rising edge of the sixth clock signal arrives, the successive approximation register determines D3; when the rising edge of the seventh clock signal arrives, the successive approximation register determines D2; when the rising edge of the eighth clock signal arrives, the successive approximation register determines D1; when the rising edge of the ninth clock signal arrives, the successive approximation register determines D0, and so far, the correction process is completed; and the values of the digital signals D7, D6, D5, D4, D3, D2, D1 and D0 are kept by the successive approximation register and used in normal operation of the comparator.

### Claim 5 (depends on 4)

The comparator offset voltage self-correction circuit of claim 4, wherein in the entire correction process, according to the comparison results of the comparator, the electric potential of the inverting input end VM of the comparator is sequentially increased or decreased by Vs/22, Vs/23, Vs/24, Vs/25, Vs/26, Vs/27, Vs/28 and Vs/28 based on Vcal, and gradually converges at Vcal; finally, the difference between VM and Vcal is only Vs/28; the smaller the Vs is, the closer the VM is to Vcal, and meanwhile, the narrower the correction range is; a higher correction digit is adopted to maintain higher correction accuracy and a wider correction range.

### Claim 6 (depends on 1)

The comparator offset voltage self-correction circuit of claim 1, wherein an actual reference voltage of the comparator is corrected to be close to Vcal and reaches certain correction accuracy; and Vcal is not affected by the comparator offset voltage, and is designable and controllable.

### Claim 7

A comparator offset voltage self-correction circuit, comprising:
a multiplexer, an offset digital adjustment amplifier, a dynamic comparator, a successive approximation register, an analog signal input port Vin, a correction signal input port Vcal, a reference signal input port Vr, a clock port, an enable port and an output port, wherein the analog signal input port Vin is configured to receive an analog signal; the correction signal input port Vcal is configured to receive a correction signal; the reference signal input port Vr is configured to receive a reference signal; the clock port is configured to receive an input clock signal; the enable port is configured to start a correction process; the output port is configured to output a comparison result; a first selection end of the multiplexer is connected to the correction signal input port Vcal, a second selection end of the multiplexer is connected to the analog signal input port Vin, and an output end of the multiplexer is connected to a non-inverting input end VP of the offset digital adjustment amplifier; an inverting input end VM of the offset digital adjustment amplifier is connected to the reference signal input port Vr; a non-inverting output end VOP of the offset digital adjustment amplifier is connected to a non-inverting input end VP of the dynamic comparator; an inverting output end VOM of the offset digital adjustment amplifier is connected to an inverting input end VM of the dynamic comparator; an output end of the dynamic comparator is connected to the output port; digital output ends D0, D1, D2, D3, D4, D5, D6 and D7 of the successive approximation register are connected to digital input ends D0, D1, D2, D3, D4, D5, D6 and D7 of the offset digital adjustment amplifier, an enable end of the successive approximation register is connected to the enable port, a clock end of the successive approximation register is connected to the clock input port, and a data end Din of the successive approximation register is connected to an output end of the dynamic comparator; the clock input port is connected to the clock ends of both the successive approximation register and the dynamic comparator; and an equivalent input offset of the offset digital adjustment amplifier is
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wherein c is a constant, gm represents a transconductance coefficient of the offset digital adjustment amplifier, R141 represents a resistance value of a resistor, and R143 represents a resistance value of a resistor.

### Claim 8 (depends on 7)

The comparator offset voltage self-correction circuit of claim 7, wherein the offset digital adjustment amplifier comprises a differential pair circuit, two symmetric load resistors, two symmetric offset adjustment resistors, two symmetric current mirrors, two symmetric current-mode digital-to-analog converters, an analog signal input port VIN, a reference signal input port VREF, non-inverting and inverting output ports VO+ and VO−, data input ports D0, D1, D2, D3, D4, D5, D6 and D7, non-inverting and inverting input ports VP and VM, non-inverting and inverting output ports VOP and VOM, and digital input ends D0, D1, D2, D3, D4, D5, D6 and D7; the differential pair circuit comprises two symmetric NMOS transistors, and a tail current source; after being connected together, source electrodes of the NMOS transistors are connected to a current input end of the tail current source; an output end of the tail current source is grounded; the gate electrode of the NMOS transistor is connected to the non-inverting input port VP; the gate electrode of the NMOS transistor is connected to the inverting input port VM; the drain electrode of the NMOS transistor is connected to the negative end of the load resistor; the positive end of the load resistor is connected to a power supply; the drain electrode of the NMOS transistor is connected to the negative end of the load resistor; the positive end of the load resistor is connected to the power supply; the positive end of the offset adjustment resistor is connected to the drain electrode of the NMOS transistor, and the negative end of the offset adjustment resistor is connected to an output end of the current mirror and the inverting output port VOM; the positive end of the offset adjustment resistor is connected to the drain electrode of the NMOS transistor, and the negative end of the offset adjustment resistor is connected to an output end of the current mirror and the non-inverting output port VO+; the current mirror comprises PMOS transistors; the current mirror comprises PMOS transistors; the gate and drain electrodes of the PMOS transistor are connected together as an input end of the current mirror, and the source electrode of the PMOS transistor is connected to the power supply; the gate electrode of the PMOS transistor is connected to that of the PMOS transistor, the source electrode of the PMOS transistor is connected to the power supply, and the drain electrode of the PMOS transistor is used as an output end of the current mirror; the gate and drain electrodes of the PMOS transistor are connected together as an input end of the current mirror, and the source electrode of the PMOS transistor is connected to the power supply; the gate electrode of the PMOS transistor is connected to that of the PMOS transistor, the source electrode of the PMOS transistor is connected to the power supply, and the drain electrode of the PMOS transistor is used as an output end of the current mirror; the current mirror mirrors input current I1 thereof to the output end according to a ratio of 1:1 to obtain output current I3, and the current mirror mirrors input current I2 thereof to the output end according to the ratio of 1:1 to obtain output current I4; an output end of the current-mode digital-to-analog converter is connected to the input end of the current mirror, and outputs the current I1; the current output end of the current-mode digital-to-analog converter is connected to the input end of the current mirror, and outputs the current I2; the current-mode digital-to-analog converter receives digital signals from the input ports D0, D1, D2, D3, D4, D5, D6 and D7; and the current-mode digital-to-analog converter receives complementary codes of the digital signals D7D6D5D4D3D2D1D0.

### Claim 9 (depends on 7)

The comparator offset voltage self-correction circuit of claim 7, wherein the dynamic comparator is of a differential structure, comprising: a preamplifier, a latch circuit, a digital portion, a bias circuit, a non-inverting input port, an inverting input port, a clock input port and an output port; the preamplifier is a differential amplifier which is configured to provide a certain differential gain to reduce a metastable effect of the dynamic comparator, and which comprises two symmetric NMOS transistors, another two symmetric NMOS transistors, two symmetric resistors, and a tail current source; the symmetric NMOS transistors form a differential pair, after being connected together, the source electrodes of the NMOS transistors are connected to a current input end of the tail current source; a current output end of the tail current source is grounded; the gate electrode of the NMOS transistor is connected to the inverting input port VM of the comparator; the gate electrode of the NMOS transistor is connected to the non-inverting input port VP of the comparator; the drain electrode of the NMOS transistor is connected to the source electrode of the NMOS transistor; the drain electrode of the NMOS transistor is connected to the source electrode of the NMOS transistor; after being connected together, the gate electrodes of the NMOS transistors are connected to the output end of the bias circuit; the drain electrode of the NMOS transistor is connected to the negative end of the resistor and outputs a voltage signal SP; the drain electrode of the NMOS transistor is connected to the negative end of the resistor 168 and outputs a voltage signal SM; the voltage signals SP and SM are a pair of differential signals, which are non-inverting and inverting signals respectively; the positive ends of the resistors are connected to the power supply; and the preamplifier amplifies the differential signals from the ports VP and VM to obtain differential signal SP and SM; the latch circuit comprises two symmetric NMOS transistors, a tail current source, two symmetric PMOS transistors, two symmetric NMOS transistors, a PMOS switching transistor, and an NMOS switching transistor; the NMOS transistors form a differential pair; after being connected together, the source electrodes of the NMOS transistors are connected to the current input end of current source; and the current output end of the current source is grounded; the gate electrode of the NMOS transistor receives the voltage signal SM; the gate electrode of the NMOS transistor receives the voltage signal SP; the PMOS transistors are cross-coupled: the gate electrode of the PMOS transistor is connected to the drain electrode of the PMOS transistor, and the gate electrode of the PMOS transistor is connected to the drain electrode of the PMOS transistor; the source electrodes of the PMOS transistors are connected to the power supply; the drain electrode of the PMOS transistor is connected to a node C, and the drain electrode of the PMOS transistor is connected to a node D; the NMOS transistors are cross-coupled: the gate electrode of the NMOS transistor is connected to the drain electrode of the NMOS transistor, and the gate electrode of the NMOS transistor is connected to the drain electrode of the NMOS transistor; the drain electrode of the NMOS transistor is connected to the node D, and the drain electrode of the NMOS transistor is connected to the node C; after being connected together, the source electrodes of the NMOS transistors are connected to the drain electrode of the NMOS switching transistor, the source electrode of the NMOS switching transistor is grounded, and the gate electrode of the NMOS switching transistor is connected to the clock input port; the source electrode of the PMOS switching transistor is connected to the node C, the drain electrode of the PMOS switching transistor is connected to the node D, and the gate electrode of the PMOS switching transistor is connected to the clock input port; the digital portion comprises two NAND gates, and an inverter; the NAND gates are cross-coupled: an output end of the NAND gate is connected to an input end of NAND gate, and an output end of NAND gate is connected to an input end of the NAND gate; and the other input end of the NAND gate is connected to the node C, and the other input end of the NAND gate is connected to the node D; an input end of the inverter is connected to the output end of the NAND gate, and an output end of the inverter is connected to the output port of the dynamic comparator; and the digital portion converts differential signals of the nodes C and D into single-ended digital signals to be output.

### Claim 10 (depends on 9)

The comparator offset voltage self-correction circuit of claim 9, wherein a working process of the latch circuit is as follows:
when the clock signal is at a low level, the NMOS switching transistor is turned off, and the cross-coupled NMOS transistors do not work as no current flows through the transistors; the PMOS switching transistor is turned on, the nodes C and D are short-circuited, and the cross-coupled PMOS transistors work as a diode as the gate electrodes and drain electrodes thereof are short-circuited;
the voltage signals SP and SM are applied on the gate electrodes of the differential pair transistors, respectively; the current of the tail current source is redistributed: when SP is greater than SM, the current flowing through the NMOS transistor is greater than the current flowing through the NMOS transistor; when SM is greater than SP, the current flowing through the NMOS transistor is greater than the current flowing through the NMOS transistor, wherein a specific distribution ratio is determined by a transconductance of the differential pair formed by the transconductance NMOS transistors;
when the rising edge of the clock signal arrives, a level of the clock signal changes from a low level to a high level; the NMOS switching transistor is turned on, and the cross-coupled NMOS transistors start to work; meanwhile, the PMOS switching transistor is turned off, the nodes C and D are disconnected, and the gate electrodes and the drain electrodes of the cross-coupled PMOS transistors are disconnected;
when the rising edge of the clock signal arrives, the voltage signal SM is greater than the voltage signal SP, the current flowing through the transistor is greater than the current flowing through the transistor; after the nodes C and D are disconnected, a voltage at the node C is pulled down, and a voltage at the node D is pulled up; the cross-coupled NMOS transistors and the cross-coupled PMOS transistors form a positive feedback mechanism through which the node C is quickly pulled to a ground potential and the node D to a power supply;
when the rising edge of the clock signal arrives, the voltage signal SP is greater than the voltage signal SM, the current flowing through the transistor is greater than the current flowing through the transistor; after the nodes C and D are disconnected, a voltage at the node D is pulled down, and a voltage at the node C is pulled up; the cross-coupled NMOS transistors and the cross-coupled PMOS transistors form a positive feedback mechanism through which the node D is quickly pulled to the ground potential and the node C to the power supply;
it can be seen that after being amplified by the preamplifier, a difference between the port signal VP and the port signal VM is latched on the rising edge of the clock signal, and is rapidly amplified to values between the ground and the power supply; that is, when VP is greater than VM, the node C obtains a power supply potential , and the node D obtains a ground potential; and when VP is smaller than VM, the node D obtains a power supply potential, and the node C obtains a ground potential.