# US 2019/0356324 A1 · PLL with Lock-in Frequency Controller

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- Number: US 2019/0356324 A1
- Document ID: US20190356324A1
- Status: Published application
- Kind: A1
- Application number: 16/413,409
- Filed: 2019-05-15
- Published: 2019-11-21
- Earliest claimed: 2018-05-15
- Assignees: Perceptia IP Pty Ltd
- Applicants: Perceptia IP Pty Ltd
- Inventors: Julian Jenkins
- Web page: https://patentgrep.com/patent/US20190356324A1

## CPC

- H03K 5/14: by the use of delay lines (H03K5/133 takes precedence)
- H03L 7/1976: {using a phase accumulator for controlling the counter or frequency divider}
- H03K 5/24: the characteristic being amplitude
- H03K 21/02: Input circuits
- H03L 7/0802: {the loop being adapted for reducing power consumption (H03L7/14 takes precedence)}
- H03L 7/081: provided with an additional controlled phase shifter {(H03L7/0998 takes precedence)}
- H03L 7/085: concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00)
- H03L 7/087: using at least two phase detectors or a frequency and phase detector in the loop
- H03L 7/093: using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence)
- H03L 7/099: concerning mainly the controlled oscillator of the loop
- H03L 7/0994: {comprising an accumulator}
- H03L 7/1806: {the frequency divider comprising a phase accumulator generating the frequency divided signal}
- H03L 7/191: using at least two different signals from the frequency divider or the counter for determining the time difference (H03L7/193, H03L7/195 take precedence)
- H03L 7/1972: {for reducing the locking time interval (H03L7/1974, H03L7/199 take precedence)}
- H03K 19/017509: {Interface arrangements}
- H03K 2005/00078: {Fixed delay}
- H03M 7/16: Conversion to or from unit-distance codes, e.g. Gray code, reflected binary code
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

A PLL has a frequency comparator that is active during lock-in. It outputs a signal related to the difference between the oscillator frequency and a target frequency. It captures an initial phase and observes change in phase relative to the initial phase. Two ways of capturing the initial phase are provided. The frequency comparator can provide input signals for the loop filter and make the PLL act as a frequency-locked loop during lock-in. Alternatively, it can provide input signals for a search controller that may perform a binary or other search. The frequency comparator may wait one or more cycles of the reference clock signal to reduce noise, or it may set a threshold to eliminate some noise. It may signal that the oscillator frequency equals the target frequency when the threshold has not been exceeded after a timeout. The search controller may directly or indirectly control the PLL's oscillator.

## Claims

### Claim 1

A phase-locked loop (PLL), comprising:
a phase predictor;
a phase subtractor; and
a frequency comparator configured to output a signal related to a difference between a target frequency and an oscillator frequency by capturing an initial phase and observing a change in phase relative to the initial phase;
wherein the frequency comparator is active during a lock-in period.

### Claim 2 (depends on 1)

The PLL of claim 1, wherein the capturing of the initial phase is performed by loading a value of a sampled phase that represents the initial phase in the phase predictor, such that subsequent predictions provided by the phase predictor include the change in phase relative to the initial phase.

### Claim 3 (depends on 1)

The PLL of claim 1, wherein the capturing of the initial phase is performed by loading a value of a phase difference into a register and wherein the change in phase relative to the initial phase is calculated by subtracting the value in the register from subsequent values of the phase difference.

### Claim 4 (depends on 1)

The PLL of claim 1, wherein the frequency comparator observes only a sign of the change in phase relative to the initial phase to determine if the oscillator frequency is higher than the target frequency.

### Claim 5 (depends on 1)

The PLL of claim 1, wherein the frequency comparator waits for one or more cycles of a reference clock signal before observing the change in phase relative to the initial phase.

### Claim 6 (depends on 1)

The PLL of claim 1, wherein the frequency comparator only outputs the signal if a magnitude of the change in phase relative to the initial phase exceeds a threshold.

### Claim 7 (depends on 6)

The PLL of claim 6, wherein the frequency comparator outputs a signal that the difference equals zero if a timeout has occurred.

### Claim 8 (depends on 1)

The PLL of claim 1, further comprising a search controller configured for finding an oscillator control signal that results in an oscillator frequency within a search margin of the target frequency using successive output signals of the frequency comparator.

### Claim 9 (depends on 8)

The PLL of claim 8, wherein the search controller finds the oscillator control signal by performing one of a binary search, a linear search, a jump search, an interpolation search, an exponential search, a Fibonacci search, and a Newton-Raphson search.

### Claim 10 (depends on 8)

The PLL of claim 8, wherein the search controller comprises a filter.

### Claim 11 (depends on 8)

The PLL of claim 8, wherein the search controller sets parameters of a loop filter.