# US 2019/0356323 A1 · PLL with Beat-Frequency Operation

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- Number: US 2019/0356323 A1
- Document ID: US20190356323A1
- Status: Published application
- Kind: A1
- Application number: 16/413,400
- Filed: 2019-05-15
- Published: 2019-11-21
- Earliest claimed: 2018-05-15
- Assignees: Perceptia IP Pty Ltd
- Applicants: Perceptia IP Pty Ltd
- Inventors: Julian Jenkins
- Web page: https://patentgrep.com/patent/US20190356323A1

## CPC

- H03K 5/14: by the use of delay lines (H03K5/133 takes precedence)
- H03L 7/1976: {using a phase accumulator for controlling the counter or frequency divider}
- H03K 5/24: the characteristic being amplitude
- H03K 21/02: Input circuits
- H03L 7/0802: {the loop being adapted for reducing power consumption (H03L7/14 takes precedence)}
- H03L 7/081: provided with an additional controlled phase shifter {(H03L7/0998 takes precedence)}
- H03L 7/085: concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00)
- H03L 7/087: using at least two phase detectors or a frequency and phase detector in the loop
- H03L 7/093: using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence)
- H03L 7/099: concerning mainly the controlled oscillator of the loop
- H03L 7/0994: {comprising an accumulator}
- H03L 7/1806: {the frequency divider comprising a phase accumulator generating the frequency divided signal}
- H03L 7/191: using at least two different signals from the frequency divider or the counter for determining the time difference (H03L7/193, H03L7/195 take precedence)
- H03L 7/1972: {for reducing the locking time interval (H03L7/1974, H03L7/199 take precedence)}
- H03K 19/017509: {Interface arrangements}
- H03K 2005/00078: {Fixed delay}
- H03M 7/16: Conversion to or from unit-distance codes, e.g. Gray code, reflected binary code
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

A PLL has a controlled oscillator with a limited frequency range. It has a phase accumulator and a phase predictor whose ranges are limited to a value K related to their bit width. K is less than the ratio of the maximum output frequency and the minimum reference frequency. The PLL locks the output frequency to a value higher than the FCW times the reference frequency. The PLL includes a means for setting the output frequency to a target frequency before achieving final lock. The PLL may have a lock detector. After acquiring lock, the PLL may reduce the bit width and K value, for example by cutting power to or switching off some of the bits, or by switching off slow counters in a multi-counter system.

## Claims

### Claim 1

A first beat-frequency PLL, comprising:
a controlled oscillator with an output clock frequency whose range is limited;
a phase accumulator comprising a modulo-K counter with a first K value related to a first bit width; and
a phase predictor with the first K value, the first bit width, and a first FCW;
wherein a maximum K value is less than a ratio of a maximum output clock frequency divided by a minimum reference clock frequency, and wherein the first beat-frequency PLL is configured to lock the output clock frequency to a value higher than the first FCW times a frequency of a reference clock signal.

### Claim 2 (depends on 1)

The first beat-frequency PLL of claim 1, wherein the output clock frequency range is fully included in a single frequency lock range (FLR).

### Claim 3 (depends on 1)

The first beat-frequency PLL of claim 1, further comprising a means for setting the output clock frequency in a target FLR prior to the first beat-frequency PLL achieving final lock.

### Claim 4 (depends on 3)

The first beat-frequency PLL of claim 3, wherein the means for setting the output clock frequency includes a frequency-lock loop, the frequency-lock loop comprising counters to measure the output clock frequency and a frequency of the reference clock signal, and a feedback loop to set the output clock frequency within a fraction of a size of the FLR to a selected integer times the first K value, plus the first FCW, times the frequency of the reference clock signal, wherein the selected integer is larger than one.

### Claim 5 (depends on 3)

The first beat-frequency PLL of claim 3, wherein the means for setting the output clock frequency includes a frequency-lock loop, the frequency-lock loop comprising counters to measure the output clock frequency and a frequency of the reference clock signal, and wherein the first beat-frequency PLL performs a search for an oscillator control code that yields a required multiplication factor between the output clock frequency and the reference clock signal frequency.

### Claim 6 (depends on 5)

The first beat-frequency PLL of claim 5, wherein the means for setting the output clock frequency includes a search controller performing one of a binary search, a linear search, a jump search, an interpolation search, an exponential search, a Fibonacci search, and a Newton-Raphson search.

### Claim 7 (depends on 3)

The first beat-frequency PLL of claim 3, wherein the means for setting the output clock frequency includes a loop filter with programmable filter parameters.

### Claim 8

A second beat-frequency PLL, comprising:
a controlled oscillator with an output clock frequency;
a modulo-K counter with a first K value related to a first bit width and a second K value related to a second bit width, wherein a modulo-K counter input is coupled with a controlled oscillator output;
a phase predictor with the first K value, the first bit width, a first frequency control word (first FCW), the second K value, the second bit width, and a second FCW; and
a lock detector configured to provide a phase lock indicator signal;
wherein, upon the phase lock indicator signal indicating that the second beat-frequency PLL is in lock, at a start of a modulo-K counter modulo-K cycle, the modulo-K counter switches from the first K value and the first bit width to the second K value and the second bit width, and the phase predictor simultaneously switches from the first K value, the first bit width and the first FCW to the second K value, the second bit width, and the second FCW.

### Claim 9 (depends on 8)

The second beat-frequency PLL of claim 8, wherein, upon the phase lock indicator signal indicating that the second beat-frequency PLL is not in lock, at the start of a modulo-K counter modulo-K cycle, the modulo-K counter switches from the second K value and the second bit width to the first K value and the first bit width, and the phase predictor simultaneously switches from the second K value, the second bit width, and the second FCW to the first K value, the first bit width and the first FCW.

### Claim 10 (depends on 8)

The second beat-frequency PLL of claim 8, wherein the first K value and the second K value are programmable.

### Claim 11 (depends on 10)

The second beat-frequency PLL of claim 10, wherein bit widths of a register and a phase comparator change simultaneously with the modulo-K counter and the phase predictor.

### Claim 12 (depends on 10)

The second beat-frequency PLL of claim 10, wherein a K-value effectively changes by one of cutting and restoring power to part of the most significant modulo-K counter bits.

### Claim 13 (depends on 10)

The second beat-frequency PLL of claim 10, wherein a K-value effectively changes by one of interrupting and restoring an input signal to part of the most significant modulo-K counter bits.

### Claim 14 (depends on 10)

The second beat-frequency PLL of claim 10, wherein the modulo-K counter comprises a fast counter and a slow counter, and a K-value changes by switching off the slow counter.

### Claim 15 (depends on 8)

The second beat-frequency PLL of claim 8, wherein the lock detector receives a phase difference and determines if successive values of the phase difference are within a narrow band around zero to indicate that the second beat-frequency PLL is in phase lock, and upon determining that the second beat-frequency PLL is in phase lock, the lock detector asserts the phase lock indicator signal.

### Claim 16 (depends on 15)

The second beat-frequency PLL of claim 15, wherein the phase lock indicator signal includes a measure of phase lock tightness and wherein the second K value, the second bit width, and the second FCW depend on the measure of phase lock tightness.

### Claim 17

A method for operating a beat-frequency PLL, comprising the following steps:
determining multiple frequency lock ranges (multiple FLRs) covering a controlled oscillator frequency range;
based on a required frequency, determining a target FLR, wherein the target FLR is one of the multiple FLRs and the target FLR includes the required frequency;
operating the controlled oscillator at a frequency in the target FLR;
determining a final K-value related to the multiple FLRs and a final FCW to generate the required frequency in the target FLR; and
simultaneously setting the final K-value and the final FCW at a start of a modulo-K counter modulo-K cycle and operating the beat-frequency PLL to generate the required frequency in the target FLR.

### Claim 18 (depends on 17)

The method of claim 17, wherein operating the controlled oscillator at a frequency in the target FLR comprises presetting the controlled oscillator at one of a highest frequency, a middle frequency, and a lowest frequency.

### Claim 19 (depends on 17)

The method of claim 17, wherein operating the controlled oscillator at a frequency in the target FLR comprises:
determining a single FLR covering the controlled oscillator frequency range;
determining an initial K-value related to the single FLR and an initial FCW to generate the required frequency in the single FLR; and
setting the initial K-value and the initial FCW and operating the beat-frequency PLL to generate the required frequency in the single FLR.

### Claim 20 (depends on 17)

The method of claim 17, wherein operating the controlled oscillator at a frequency in the target FLR comprises comparing a ratio of an output clock frequency and a reference frequency and using a search algorithm to determine an oscillator control code that yields the frequency in the target FLR, and wherein the search algorithm includes one of a binary search, a linear search, a jump search, an interpolation search, an exponential search, a Fibonacci search, and a Newton-Raphson search.

### Claim 21 (depends on 17)

The method of claim 17, wherein determining the final K-value related to the multiple FLRs and the final FCW comprises using the formula fDCO/fREF=FCW+(li−1)*K, with li ∈ {1, 2, . . . }.