# US 2019/0356316 A1 · Technology mapping method of an fpga > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0356316 A1 - Document ID: US20190356316A1 - Status: Published application - Kind: A1 - Application number: 16/529,669 - Filed: 2019-08-01 - Published: 2019-11-21 - Earliest claimed: 2017-03-28 - Assignees: SK hynix Inc.; Industry-Academic Cooperation Foundation, Yonsei University - Applicants: SK hynix Inc.; Industry-Academic Cooperation Foundation, Yonsei University - Inventors: Kangwook JO; Jeongbin KIM; Minyoung IM; Taehee YOU; Eui-Young CHUNG; Hongil YOON - Web page: https://patentgrep.com/patent/US20190356316A1 ## CPC - H03K 19/1776: for memories - G06F 30/327: Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist - G06F 30/34: for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD] - G06F 30/343: Logical level - H03K 19/0013: {in field effect transistor circuits} - H03K 19/1731: {Optimisation thereof} - H03K 19/17744: {for input/output signals} - H03K 19/20: characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) - G11C 11/1673: {Reading or sensing circuits or methods} - G11C 11/1675: {Writing or programming circuits or methods} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A technology mapping method for a FPGA includes converting a gate level netlist into an AND-Inverter Graph (AIG) netlist, selecting a node among nodes included in the AIG netlist, generating a cut set including one or more cuts corresponding to the selected node, selecting a best cut by sorting the cuts included in the cut set according to predetermined criteria and outputting a LUT netlist including the best cut, wherein the predetermined criteria include a maximum difference of levels of sub-cuts connected in each cut as a first criterion. ## Claims ### Claim 1 A technology mapping method for a FPGA, comprising: converting a gate level netlist into an AND-Inverter Graph (AIG) netlist; selecting a node among nodes included in the AIG netlist; generating a cut set including one or more cuts corresponding to the selected node; selecting a best cut by sorting the cuts included in the cut set according to predetermined criteria; and outputting a LUT netlist including the best cut, wherein the predetermined criteria include a maximum difference of levels of sub-cuts connected in each cut as a first criterion. ### Claim 2 (depends on 1) The technology mapping method of claim 1, wherein the predetermined criteria comprise a delay amount corresponding to a cut, as a second criterion, and an area corresponding to a cut, as a third criterion, and wherein the second criterion is applied to cuts having the same delays and the third criterion is applied to cuts having the same areas, the cuts having the same delays being determined according to the first criterion, the cuts having the same areas being determined according to the second criterion. ### Claim 3 (depends on 1) The technology mapping method of claim 1, wherein the FPGA includes: a plurality of first LUTs each configured to output a first output signal according to programming states of magnetic elements corresponding to a first input signal during a first time period; and a plurality of second LUTs each configured to output a second output signal according to programming states of magnetic elements corresponding to a second input signal during a second time period. ### Claim 4 (depends on 3) The technology mapping method of claim 3, further comprising: matching each LUT in the LUT netlist with one of the plurality of first LUTs or one of the plurality of second LUTs according to a level of each LUT so that difference between number of LUTs in the LUT netlist matched to first LUTs and number of LUTs in the LUT netlist matched to second LUTs is minimized. ### Claim 5 (depends on 4) The technology mapping method of claim 4, wherein LUTs in the netlist having same level are matched to either first LUTs or second LUTs. ### Claim 6 (depends on 3) The technology mapping method of claim 3, wherein each of the plurality of first LUTs comprises: a decoder configured to decode the first input signal and to output decoded signals; a storage unit including a plurality of magnetic elements, the storage unit being configured to select one or more of the plurality of magnetic elements in response to the decoded signals; and a signal IO unit configured to output the first output signal corresponding to the selected one or more magnetic elements, and to receive a write signal to program the selected one or more magnetic elements. ### Claim 7 (depends on 6) The technology mapping method of claim 6, wherein the storage unit comprises: a first storage unit connected between a first terminal and a second terminal and configured to select a magnetic element according to an inverted decoded signal, the inverted decoded signal being an inversion of an activated decoded signal among the decoded signals; and a second storage unit connected between a third terminal and a fourth terminal and configured to select a magnetic element according to the activated decoded signal, wherein the signal IO unit comprises a first PMOS transistor and a first NMOS transistor connected in series between the second terminal and the third terminal, drains of the first PMOS transistor and the first NMOS transistor are commonly connected to a first node, and a signal is input or output via the first node, and wherein the signal IO control unit is configured to control gates of the first PMOS transistor and the first NMOS transistor in order to maintain a level of the first output signal for the second time period after the first time period has elapsed. ### Claim 8 (depends on 3) The technology mapping method of claim 3, wherein each of the plurality of second LUTs comprises: a decoder configured to decode the second input signal and to output decoded signals; a storage unit including a plurality of magnetic elements, the storage unit being configured to select one or more of the plurality of magnetic elements in response to the decoded signals; and a signal IO unit configured to output the second output signal corresponding to the selected one or more magnetic elements, and to program the selected one or more magnetic elements by receiving a write signal. ### Claim 9 (depends on 7) The technology mapping method of claim 7, wherein the storage unit comprises: a first storage unit connected between a first terminal and a second terminal and configured to select a magnetic element according to an inverted decoded signal, the inverted decoded signal being an inversion of an activated decoded signal among the decoded signals; and a second storage unit connected between a third terminal and a fourth terminal and configured to select a magnetic element according to the activated decoded signal, wherein the signal IO unit comprises a first PMOS transistor and a first NMOS transistor connected in series between the second terminal and the third terminal, drains of the first PMOS transistor and the first NMOS transistor are commonly connected to a first node, and a signal is input or output via the first node, and wherein the signal IO control unit is configured to control gates of the first PMOS transistor and the first NMOS transistor in order to maintain a level of the second output signal for the first time period after the second time period has elapsed. ### Claim 10 (depends on 3) The technology mapping method of claim 3, wherein the first time period corresponds to a time period when a clock signal is at a high level and the second time period corresponds to a time period when the clock signal is at a low level.