# US 2019/0356306 A1 · Apparatus and method for interpolating between a first and a second signal > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0356306 A1 - Document ID: US20190356306A1 - Status: Published application - Kind: A1 - Application number: 16/474,560 - Filed: 2017-03-31 - Published: 2019-11-21 - Earliest claimed: 2017-03-31 - Assignees: Apple Inc. - Applicants: Intel IP Corporation - Inventors: Georgios Palaskas; Sebastian Sievert - Web page: https://patentgrep.com/patent/US20190356306A1 ## CPC - H03K 5/13: Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals - G04F 10/06: by measuring phase {(G04F10/005 takes precedence)} - H03M 1/00: Analogue/digital conversion; Digital/analogue conversion (conversion of analogue values to or from differential modulation H03M3/00) - H03K 2005/00052: {by mixing the outputs of fixed delayed signals with each other or with the input signal} - H04L 25/03: Shaping networks in transmitter or receiver, e.g. adaptive shaping networks - H04W 84/042: {Public Land Mobile systems, e.g. cellular systems} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - G04F: TIME-INTERVAL MEASURING (measuring pulse characteristics G01R, e.g. G01R29/02; in radar or like systems G01S) - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) - H04W: WIRELESS COMMUNICATION NETWORKS (broadcast communication H04H; communication systems using wireless links for non-selective communication, e.g. wireless extensions H04M1/72) ## Abstract An apparatus for interpolating between a first and a second signal is provided. The apparatus includes a plurality of interpolation cells coupled to a common node of the apparatus. Further, the apparatus includes a control circuit configured to supply, based on a control word, respective selection signals to each of the plurality of interpolation cells. At least one of the plurality of interpolation cells is configured to couple the common node to a first potential if the first signal and the second signal are both at a first signal level, couple the common node to a second potential, which is different from the first potential, if the first signal and the second signal are both at a second signal level, which is different from the first signal level, and to decouple the common node from at least one of the first potential and the second potential if the first signal and the second signal are at different signal levels. Additionally, the at least one of the plurality of interpolation cells is configured to switch, based on a state indicated by the respective selection signal, to coupling the common node to the second potential in response to a transition of either the leading one or the trailing one of the first signal and the second signal from the first signal level to the second signal level. ## Claims ### Claim at position 1 1-25. (canceled) ### Claim 26 An apparatus for interpolating between a first and a second signal, comprising: a plurality of interpolation cells coupled to a common node of the apparatus; and a control circuit configured to supply, based on a control word, respective selection signals to each of the plurality of interpolation cells, wherein at least one of the plurality of interpolation cells is configured to: couple the common node to a first potential if the first signal and the second signal are both at a first signal level, couple the common node to a second potential, which is different from the first potential, if the first signal and the second signal are both at a second signal level, which is different from the first level, and to decouple the common node from at least one of the first potential and the second potential if the first signal and the second signal are at different signal levels; and switch, based on a state indicated by the respective selection signal, to coupling the common node to the second potential in response to a transition of either the leading one or the trailing one of the first signal and the second signal from the first signal level to the second signal level. ### Claim 27 (depends on 26) The apparatus of claim 26, wherein the at least one of the plurality of interpolation cells is further configured to: switch to coupling the common node to the second potential in response to the transition of the trailing one of the first signal and the second signal from the first signal level to the second signal level, if the selection signal indicates a first state; or switch to coupling the common node to the second potential in response to the transition of the leading one of the first signal and the second signal from the first signal level to the second signal level, if the selection signal indicates a different second state. ### Claim 28 (depends on 26) The apparatus of claim 26, wherein the at least one of the plurality of interpolation cells is further configured to: switch, based on the state indicated by the respective selection signal, to coupling the common node to the first potential in response to a subsequent transition of either the leading one or the trailing one of the first signal and the second signal from the second signal level to the first signal level. ### Claim 29 (depends on 28) The apparatus of claim 28, wherein the at least one of the plurality of interpolation cells is further configured to: switch to coupling the common node to the first potential in response to the transition of the trailing one of the first signal and the second signal from the second signal level to the first signal level, if the selection signal indicates a first state; or switch to coupling the common node to the first potential in response to the transition of the leading one of the first signal and the second signal from the second signal level to the first signal level, if the selection signal indicates a different second state. ### Claim 30 (depends on 26) The apparatus of claim 26, wherein the at least one of the plurality of interpolation cells comprises: a first pull-up/down path comprising a first plurality of transistors coupled between the first potential and the second potential, wherein the first pull-up/down path is configured to couple the common node to one of the first potential and the second potential if the selection signal indicates a first state; and a second pull-up/down path comprising a second plurality of transistors coupled between the first potential and the second potential, wherein the second pull-up/down path is configured to couple the common node to one of the first potential and the second potential if the selection signal indicates a different second state. ### Claim 31 (depends on 30) The apparatus of claim 30, wherein the first pull-up/down path comprises: a first transistor stack of a first conductivity type which is coupled between the first potential and a first node, wherein the first transistor stack is configured to receive the leading one of the first signal and the second signal, the trailing one of the first signal and the second signal, and the inverted selection signal at respective transistor control terminals of the first transistor stack; a second transistor stack of a different second conductivity type which is coupled between the second potential and the first node, wherein the second transistor stack is configured to receive the leading one of the first signal and the second signal, the trailing one of the first signal and the second signal, and the selection signal at respective transistor control terminals of the second transistor stack, wherein the first node is coupled to the common node. ### Claim 32 (depends on 30) The apparatus of claim 30, wherein the second pull-up/down path comprises: a third transistor stack of the first conductivity type which is coupled between the first potential and a second node, wherein the third transistor stack is configured to receive a third signal, the leading one of the first signal and the second signal, and the selection signal at respective transistor control terminals of the third transistor stack; and a fourth transistor stack of the second conductivity type which is coupled between the second potential and the second node, wherein the fourth transistor stack is configured to receive a fourth signal, the leading one of the first signal and the second signal, and the inverted selection signal at respective transistor control terminals of the fourth transistor stack, wherein the second node is coupled to the common node. ### Claim 33 (depends on 26) The apparatus of claim 26, further comprising: a selection circuit configured to select the leading one of the first signal and the second signal, and to supply it to a first input node of the one of the plurality of interpolation cells that is dedicated to the leading one of the first signal and the second signal, wherein the selection circuit is further configured to select the trailing one of the first signal and the second signal, and to supply it to a second input node of the one of the plurality of interpolation cells that is dedicated to the trailing one of the first signal and the second signal. ### Claim 34 (depends on 33) The apparatus of claim 33, wherein the selection circuit comprises a plurality of multiplexers. ### Claim 35 (depends on 30) The apparatus of claim 30, wherein the at least one of the plurality of interpolation cells further comprises: a first selection circuit configured to supply, based on a timing signal that indicates the temporal order of the first signal and the second signal, either the first signal or a third signal as a first selected signal to the first pull-up/down path; and a second selection circuit configured to supply, based on the timing signal, either the first signal or a fourth signal as a second selected signal to the first pull-up/down path. ### Claim 36 (depends on 35) The apparatus of claim 35, wherein the first pull-up/down path comprises: a first transistor stack of a first conductivity type which is coupled between the first potential and a first node, wherein the first transistor stack is configured to receive the second signal, the first selected signal and the inverted selection signal at respective transistor control terminals of the first transistor stack; and a second transistor stack of a different second conductivity type which is coupled between the second potential and the first node, wherein the second transistor stack is configured to receive the second signal, the second selected signal and the selection signal at respective transistor control terminals of the second transistor stack, wherein the first node is coupled to the common node. ### Claim 37 (depends on 35) The apparatus of claim 35, wherein the first selection circuit is further configured to supply, based on the timing signal, either the second signal or the third signal as a third selected signal to the second pull-up/down path, and wherein the second selection circuit is further configured to supply, based on the timing signal, either the second signal or the fourth signal as a fourth selected signal to the second pull-up/down path. ### Claim 38 (depends on 37) The apparatus of claim 37, wherein the second pull-up/down path comprises: a third transistor stack of the first conductivity type which is coupled between the first potential and a second node, wherein the third transistor stack is configured to receive the first signal, the third selected signal and the selection signal at respective transistor control terminals of the third transistor stack; and a fourth transistor stack of the second conductivity type which is coupled between the second potential and the second node, wherein the fourth transistor stack is configured to receive the first signal, the fourth selected signal and the inverted selection signal at respective transistor control terminals of the fourth transistor stack, wherein the second node is coupled to the common node. ### Claim 39 (depends on 35) The apparatus of claim 35, wherein the first selection circuit comprises a first multiplexer configured to select, based on the timing signal, either the first signal or the third signal as the first selected signal, and wherein the second selection circuit comprises a second multiplexer configured to select, based on the timing signal, either the first signal or the fourth signal as the second selected signal. ### Claim 40 (depends on 39) The apparatus of claim 39, wherein the first multiplexer consists of a first and a second transistor of a second conductivity type that are coupled in parallel to an output node of the first multiplexer, wherein the first transistor is configured to receive the inverted timing signal at its control terminal and to receive the first signal at another terminal, and wherein the second transistor is configured to receive the timing signal at its control terminal and to receive the third signal at another terminal. ### Claim 41 (depends on 39) The apparatus of claim 39, wherein the second multiplexer consists of a third and a fourth transistor of a first conductivity type that are coupled in parallel to an output node of the second multiplexer, wherein the third transistor is configured to receive the timing signal at its control terminal and to receive the first signal at another terminal, and wherein the fourth transistor is configured to receive the inverted timing signal at its control terminal and to receive the fourth signal at another terminal. ### Claim 42 (depends on 32) The apparatus of claim 32, wherein the third signal is a constant third potential, and wherein the fourth signal is a constant fourth potential. ### Claim 43 (depends on 32) The apparatus of claim 32, wherein the first signal and the second signal are oscillation signals, and wherein the third signal and the fourth signal are an oscillation signal that leads the leading one of the first signal and the second signal by a fraction of the oscillation period of the first signal. ### Claim 44 (depends on 26) The apparatus of claim 26, further comprising a frequency divider circuit configured to generate the first signal and the second signal based on an oscillation signal. ### Claim 45 (depends on 26) A digital-to-time converter comprising an apparatus for interpolating between a first signal and a second signal according to claim 26. ### Claim 46 A method for interpolating between a first and a second signal using a plurality of interpolation cells coupled to a common node, comprising: supplying, based on a control word, respective selection signals to each of the plurality of interpolation cells; coupling, by at least one of the plurality of interpolation cells, the common node to a first potential if the first signal and the second signal are both at a first signal level; coupling, by the at least one of the plurality of interpolation cells, the common node to a second potential, which is different from the first potential, if the first signal and the second signal are both at a second signal level, which is different from the first signal level; decoupling, by the at least one of the plurality of interpolation cells, the common node from at least one of the first potential and the second potential if the first signal and the second signal are at different signal levels; and switching, by the at least one of the plurality of interpolation cells and based on a state indicated by the respective selection signal, to coupling the common node to the second potential in response to a transition of either the leading one or the trailing one of the first signal and the second signal from the first signal level to the second signal level. ### Claim 47 (depends on 46) The method of claim 46, switching to coupling the common node to the second potential comprises: switching to coupling the common node to the second potential in response to the transition of the trailing one of the first signal and the second signal from the first signal level to the second signal level, if the selection signal indicates a first state; or switching to coupling the common node to the second potential in response to the transition of the leading one of the first signal and the second signal from the first signal level to the second signal level, if the selection signal indicates a different second state. ### Claim 48 (depends on 46) The method of claim 46, wherein the method further comprises: switching, based on the state indicated by the respective selection signal, to coupling the common node to the first potential in response to a subsequent transition of either the leading one or the trailing one of the first signal and the second signal from the second signal level to the first signal level. ### Claim 49 (depends on 48) The method of claim 48, wherein switching to coupling the common node to the first potential comprises: switching to coupling the common node to the first potential in response to the transition of the trailing one of the first signal and the second signal from the second signal level to the first signal level, if the selection signal indicates a first state; or switching to coupling the common node to the first potential in response to the transition of the leading one of the first signal and the second signal from the second signal level to the first signal level, if the selection signal indicates a different second state. ### Claim 50 (depends on 46) The method of claim 46, further comprising: selecting the leading one of the first signal and the second signal; supplying the leading one of the first signal and the second signal to a first input node of the one of the plurality of interpolation cells that is dedicated to the leading one of the first signal and the second signal; selecting the trailing one of the first signal and the second signal; and supplying the trailing one of the first signal and the second signal to a second input node of the one of the plurality of interpolation cells that is dedicated to the trailing one of the first signal and the second signal.