# US 2019/0356286 A1 · Power density matching circuits for power amplifiers

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- Number: US 2019/0356286 A1
- Document ID: US20190356286A1
- Status: Published application
- Kind: A1
- Application number: 16/431,644
- Filed: 2019-06-04
- Published: 2019-11-21
- Earliest claimed: 2014-10-21
- Assignees: Skyworks Solutions, Inc.
- Applicants: Skyworks Solutions, Inc.
- Inventors: Anatoli PUKHOVSKI
- Web page: https://patentgrep.com/patent/US20190356286A1

## CPC

- H03F 3/211: {using a combination of several amplifiers (H03F3/60 takes precedence)}
- H03F 1/0261: {with control of the polarisation voltage or current, e.g. gliding Class A}
- H03F 3/19: with semiconductor devices only
- H03F 3/45475: {using IC blocks as the active amplifying circuit}
- H03F 2200/18: the bias of the gate of a FET being controlled by a control signal
- H03F 2200/451: the amplifier being a radio frequency amplifier
- H03F 2203/21145: Output signals are combined by switching a plurality of paralleled power amplifiers to a common output
- H03F 2203/45154: the bias at the input of the amplifying transistors being controlled
- H03F: AMPLIFIERS

## Abstract

Circuits and methods related to power amplifiers. Power density matching circuits can be provided to match power densities in reference devices and amplifying devices. In some implementations, a power density matching circuit includes a temperature independent current translator with a first transistor and a third transistor coupled emitter to collector between a power supply node and ground and a second transistor and a fourth transistor coupled emitter to collector between the power supply node and ground. The transistors of the current translator can be sized relative to one another to set a current density in the amplifying transistor relative to a current density in the reference transistor. The current translation can provide power density matching between the amplifying transistor and the reference transistor.

## Claims

### Claim 1

A power density matching circuit configured to match power density changes between an amplifying transistor and a reference transistor, the circuit comprising:
a supply node configured to receive a supply voltage;
a differential node configured to receive a signal from a differential amplifier;
a reference node configured to provide a bias signal to the reference transistor;
an amplifying node configured to provide a bias signal to the amplifying transistor; and
a temperature independent current translator with a first transistor and a third transistor coupled emitter to collector between the supply node and a ground and a second transistor and a fourth transistor coupled emitter to collector between the supply node and the ground, a collector of the first transistor coupled to the supply node, a base of the first transistor coupled to the differential node, a base of the third transistor coupled to a collector of the third transistor, an emitter of the third transistor coupled to the ground, a collector of the second transistor coupled to the supply node, a base of the second transistor coupled to the differential node, a base of the fourth transistor coupled to a collector of the fourth transistor and to the reference node, and an emitter of the fourth transistor coupled to the ground.

### Claim 2 (depends on 1)

The power density matching circuit of claim 1 wherein temperature independent current translation provides power density matching between the amplifying transistor and the reference transistor.

### Claim 3 (depends on 2)

The power density matching circuit of claim 2 wherein the sizes of the first transistor, the second transistor, the third transistor, and the fourth transistor are provided according to a sizing equation given by the following:
I
PA
=
I
ref

E
PA
E
ref

E
2

E
3
E
1

E
4
wherein the sizing equation relates a current of the amplifying transistor (IPA) to a current of the reference transistor (Iref), an emitter area of the reference transistor (Eref), an emitter area of the amplifying transistor (EPA), an emitter area of the first transistor (E1), an emitter area of the second transistor (E2), an emitter area of the third transistor (E3), and an emitter area of the fourth transistor (E4).

### Claim 4 (depends on 3)

The power density matching circuit of claim 3 wherein a current density in the amplifying transistor relative to the reference transistor (JPA/ref) is given by a square root of ((E2E3)/(E1E4)).

### Claim 5 (depends on 4)

The power density matching circuit of claim 4 wherein JPA/ref=2 and E4=4E1=4E2=4E3.

### Claim 6 (depends on 1)

The power density matching circuit of claim 1 wherein the power density matching circuit is configured to set a first power density associated with the reference transistor and to set a second power density associated with the amplifying transistor.

### Claim 7 (depends on 6)

The power density matching circuit of claim 6 wherein the first power density is a function of a reference voltage level provided to the reference transistor.

### Claim 8 (depends on 7)

The power density matching circuit of claim 7 wherein the second power density is a function of the supply voltage received at the supply node.

### Claim 9 (depends on 8)

The power density matching circuit of claim 8 wherein the reference voltage level is less than the supply voltage.

### Claim 10 (depends on 1)

The power density matching circuit of claim 1 further comprising an inductor coupled to the amplifying node.

### Claim 11 (depends on 1)

The power density matching circuit of claim 1 wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are each sized relative to one another to set a current density in the amplifying transistor relative to a current density in the reference transistor.

### Claim 12

A semiconductor die comprising:
a packaging substrate configured to receive a plurality of components;
a plurality of connection pads formed on the packaging substrate; and
a power density matching circuit including a supply node configured to receive a supply voltage; a differential node configured to receive a signal from a differential amplifier; a reference node configured to provide a bias signal to a reference transistor; an amplifying node configured to provide a bias signal to an amplifying transistor; and a temperature independent current translator with a first transistor and a third transistor coupled emitter to collector between the supply node and a ground and a second transistor and a fourth transistor coupled emitter to collector between the supply node and the ground, a collector of the first transistor coupled to the supply node, a base of the first transistor coupled to the differential node, a base of the third transistor coupled to a collector of the third transistor, an emitter of the third transistor coupled to the ground, a collector of the second transistor coupled to the supply node, a base of the second transistor coupled to the differential node, a base of the fourth transistor coupled to a collector of the fourth transistor and to the reference node, and an emitter of the fourth transistor coupled to the ground.

### Claim 13 (depends on 12)

The semiconductor die of claim 12 wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are each sized relative to one another to set a current density in the amplifying transistor relative to a current density in the reference transistor.

### Claim 14 (depends on 12)

The semiconductor die of claim 12 wherein temperature independent current translation provides power density matching between the amplifying transistor and the reference transistor.

### Claim 15 (depends on 12)

The semiconductor die of claim 12 further comprising an inductor coupled to the amplifying node.

### Claim 16 (depends on 12)

The semiconductor die of claim 12 wherein the power density matching circuit is configured to set a first power density associated with the reference transistor and to set a second power density associated with the amplifying transistor.

### Claim 17

A wireless device comprising:
a transceiver configured to process radio-frequency signals;
an antenna in communication with the transceiver configured to facilitate transmission of an amplified radio-frequency signal; and
a power amplifier module connected to the transceiver and configured to generate the amplified radio-frequency signal, the power amplifier module including a supply node configured to receive a supply voltage; a differential node configured to receive a signal from a differential amplifier; a reference node configured to provide a bias signal to a reference transistor; an amplifying node configured to provide a bias signal to an amplifying transistor; and a temperature independent current translator with a first transistor and a third transistor coupled emitter to collector between the supply node and a ground and a second transistor and a fourth transistor coupled emitter to collector between the supply node and the ground, a collector of the first transistor coupled to the supply node, a base of the first transistor coupled to the differential node, a base of the third transistor coupled to a collector of the third transistor, an emitter of the third transistor coupled to the ground, a collector of the second transistor coupled to the supply node, a base of the second transistor coupled to the differential node, a base of the fourth transistor coupled to a collector of the fourth transistor and to the reference node, and an emitter of the fourth transistor coupled to the ground.

### Claim 18 (depends on 17)

The wireless device of claim 17 wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are each sized relative to one another to set a current density in the amplifying transistor relative to a current density in the reference transistor.

### Claim 19 (depends on 17)

The wireless device of claim 17 wherein temperature independent current translation provides power density matching between the amplifying transistor and the reference transistor.

### Claim 20 (depends on 17)

The wireless device of claim 17 wherein the power density matching circuit is configured to set a first power density associated with the reference transistor and to set a second power density associated with the amplifying transistor.