# US 2019/0356271 A1 · Common-Mode Loop Controlled Fully-Differential Adaptive Class-A Amplifier > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0356271 A1 - Document ID: US20190356271A1 - Status: Published application - Kind: A1 - Application number: 15/983,287 - Filed: 2018-05-18 - Published: 2019-11-21 - Earliest claimed: 2018-05-18 - Assignees: STMicroelectronics (Grenoble 2) SAS - Applicants: STMicroelectronics (Grenoble 2) SAS - Inventors: Flavia Amorosa; Serge Ramet; Daniel Subiela - Web page: https://patentgrep.com/patent/US20190356271A1 ## CPC - H03F 1/0205: {in transistor amplifiers} - H03F 3/19: with semiconductor devices only - H03F 3/45179: {using MOSFET transistors as the active amplifying circuit (H03F3/45278 takes precedence)} - H03F 3/45197: {Pl types (H03F3/45224, H03F3/45251 take precedence)} - H03F 3/45659: {Controlling the loading circuit of the differential amplifier} - H04B 1/1027: {assessing signal quality or detecting noise/interference for the received signal} - H04B 1/18: Input circuits, e.g. for coupling to an antenna or a transmission line (coupling networks between antennas or lines and receivers independent of the nature of the receiver H03H) - H04L 27/14: Demodulator circuits; Receiver circuits - H03F 2200/171: A filter circuit coupled to the output of an amplifier - H03F 2200/294: the amplifier being a low noise amplifier [LNA] - H03F 2200/451: the amplifier being a radio frequency amplifier - H03F 2203/45134: the whole differential amplifier together with other coupled stages being fully differential realised - H03F 2203/45526: the FBC comprising a resistor-capacitor combination and being coupled between the LC and the IC - H03F 2203/45544: the IC comprising one or more capacitors, e.g. coupling capacitors - H03F: AMPLIFIERS - H04B: TRANSMISSION - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract In an embodiment, a differential amplifier includes: an input stage; an output stage coupled to the input stage, the output stage having first and second output terminals; and a feedback circuit coupled to the output stage, where the feedback circuit is configured to dynamically adjust a bias current of the output stage based on voltages of the first and second output terminals. ## Claims ### Claim 1 A differential amplifier comprising: an input stage; an output stage coupled to the input stage, the output stage having first and second output terminals; and a feedback circuit coupled to the output stage, wherein the feedback circuit is configured to dynamically adjust a bias current of the output stage based on voltages of the first and second output terminals, wherein the output stage further comprises: a first output device coupled to the first output terminal, and a second output device coupled to the second output terminal, wherein the bias current comprises a first bias current flowing through the first output device and a second bias current flowing through the second output device. ### Claim 2 (canceled) ### Claim 3 (depends on 1) The differential amplifier of claim 1, wherein the first output device comprises a first transistor and the second output device comprises a second transistor. ### Claim 4 (depends on 3) The differential amplifier of claim 3, wherein the output stage further comprises a third transistor coupled to the first transistor, and a fourth transistor coupled to the second transistor, and wherein the feedback circuit adjusts the first bias current and the second bias current by controlling control terminals of the second and fourth transistors. ### Claim 5 (depends on 4) The differential amplifier of claim 4, wherein the first transistor and the second transistor are p-type transistors, and wherein the third transistor and the fourth transistor are n-type transistors. ### Claim 6 A differential amplifier comprising: an input stage; an output stage coupled to the input stage, the output stage having first and second output terminals; and a feedback circuit coupled to the output stage, wherein the feedback circuit is configured to dynamically adjust a bias current of the output stage based on voltages of the first and second output terminals, wherein the feedback circuit is configured to increase the bias current when a common mode voltage at the first and second output terminals increases, wherein the feedback circuit comprises: a resistive network configured to generate a first voltage; and a comparator circuit configured to compare the first voltage with a reference voltage, and generate a first output based on the comparison, the first output configured to control the bias current. ### Claim 7 (depends on 1) The differential amplifier of claim 1, wherein the feedback circuit is configured to increase the bias current when a common mode voltage at the first and second output terminals is greater than a reference voltage. ### Claim 8 (depends on 1) The differential amplifier of claim 1, wherein the output stage is configured to deliver an output current to a load, and wherein the feedback circuit is configured to increase the bias current when an output current flowing through the load is greater than a quiescent current. ### Claim 9 (depends on 8) The differential amplifier of claim 8, wherein the quiescent current is a current flowing through an output device of the output stage when the output current is about zero amperes. ### Claim 10 (depends on 8) The differential amplifier of claim 8, wherein the quiescent current is lower than 25% of a maximum output current. ### Claim 11 (depends on 1) The differential amplifier of claim 1, wherein the feedback circuit comprises: a resistive network configured to generate a first voltage; and a comparator circuit configured to compare the first voltage with a reference voltage, and generate a first output based on the comparison, the first output configured to control the bias current. ### Claim 12 (depends on 11) The differential amplifier of claim 11, wherein the resistive network comprises capacitors. ### Claim 13 (depends on 11) The differential amplifier of claim 11, wherein the feedback circuit generates the first voltage according to V   1 = V out   p + V outm 2 , wherein V1 is the first voltage, Voutp is a voltage at the first output terminal, and Voutm is a voltage at the second output terminal. ### Claim 14 A method comprising: receiving a differential input signal at an input stage of a differential amplifier; generating a differential output signal at an output stage of the differential amplifier based on the differential input signal; and dynamically adjusting a bias current of the output stage based on a common mode voltage of the differential output signal, wherein the bias current comprises a first bias current flowing through a first transistor coupled to a first output device of the output stage, the first output device coupled to a first output terminal, and a second bias current flowing through a second transistor coupled to a second output device of the output stage, the second output device coupled to a second output terminal, and wherein dynamically adjusting the bias current comprises controlling control terminals of the first and second transistors. ### Claim 15 (canceled) ### Claim 16 A method comprising: receiving a differential input signal at an input stage of a differential amplifier; generating a differential output signal at an output stage of the differential amplifier based on the differential input signal; and dynamically adjusting a bias current of the output stage based on a common mode voltage of the differential output signal, wherein dynamically adjusting the bias current comprises increasing the bias current when the common mode voltage increases. ### Claim 17 (depends on 14) The method of claim 14, wherein dynamically adjusting the bias current comprises: comparing the common mode voltage with a reference voltage; and increasing the bias current when the common mode voltage is higher than the reference voltage. ### Claim 18 (depends on 14) The method of claim 14, further comprising delivering an output current to a load, wherein dynamically adjusting the bias current comprises increasing the bias current when the output current is higher than a quiescent current. ### Claim 19 (depends on 18) The method of claim 18, wherein the quiescent current is a current flowing through an output device of the output stage when the output current is about zero amperes. ### Claim 20 (depends on 18) The method of claim 18, wherein the quiescent current is lower than 25% of a maximum output current. ### Claim 21 A radio frequency (RF) receiver comprising: a low noise amplifier configured to be coupled to an antenna; a mixer circuit coupled to the low noise amplifier; a transimpedance amplifier (TIA) stage coupled to the mixer circuit; a complex bandpass polyphaser filter (CBPF) stage coupled to the TIA stage; and an analog-to-digital converter (ADC) coupled to the CBPF stage, wherein the TIA stage comprises a differential amplifier comprising: an input stage, an output stage coupled to the input stage, the output stage having first and second output terminals, and a feedback circuit coupled to the output stage, wherein the feedback circuit is configured to dynamically adjust a bias current of the output stage based on voltages of the first and second output terminals. ### Claim 22 (depends on 21) The RF receiver of claim 21, wherein the RF receiver is configured to receive frequency modulated signals from the antenna. ### Claim 23 (depends on 22) The RF receiver of claim 22, wherein the frequency modulated signals are frequency shift keying (FSK) or Gaussian FSK (GFSK) signals. ### Claim 24 (depends on 21) The RF receiver of claim 21, wherein the feedback circuit is configured to increase the bias current when a common mode voltage at the first and second output terminals increases. ### Claim 25 (canceled) ### Claim 26 (depends on 6) The differential amplifier of claim 6, wherein the output stage further comprises a first transistor coupled to the first output terminal, and a second transistor coupled to the second output terminal, and wherein the bias current comprises a first bias current flowing through the first transistor and a second bias current flowing through the second transistor.