# US 2019/0356129 A1 · Stacked switch circuit having shoot through current protection

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- Number: US 2019/0356129 A1
- Document ID: US20190356129A1
- Status: Published application
- Kind: A1
- Application number: 16/195,616
- Filed: 2018-11-19
- Published: 2019-11-21
- Earliest claimed: 2016-06-27
- Assignees: Intel IP Corporation
- Applicants: Intel IP Corporation
- Inventors: Marian HULUB; Marcin DANIEL
- Web page: https://patentgrep.com/patent/US20190356129A1

## CPC

- H02H 11/007: {involving automatic switching for adapting the protected apparatus to the supply voltage}
- G06F 1/28: Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
- H03K 19/00361: {in field effect transistor circuits}
- H10D 99/00: Subject matter not provided for in other groups of this subclass
- H02H: EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS (indicating or signalling undesired working conditions G01R, e.g. G01R31/00, G08B; locating faults along lines G01R31/08; emergency protective devices H01H)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

An apparatus is described. The apparatus includes a stacked switch circuit having protection circuitry to prevent shoot through current when the switch is in an off state and respective voltages at the terminals of the switch change such that before the change one of the terminals of the switch has the higher voltage and after the change the other terminal of the switch has the higher voltage.

## Claims

### Claim 1

An apparatus, comprising:
a stacked switch circuit having protection circuitry to prevent shoot through current when the switch is in an off state and respective voltages at the terminals of the switch change such that before the change one of the terminals of the switch has the higher voltage and after the change the other terminal of the switch has the higher voltage.

### Claim 2 (depends on 1)

The apparatus of claim 1 wherein the protection circuitry keeps at least one of the transistors in the switch's current path off during the switch.

### Claim 3 (depends on 2)

The apparatus of claim 2 wherein when the stacked switch circuit is in the off state the protection circuitry keeps off a transistor in the switch's current path that was off in a first steady state when the one terminal of the switch had the higher voltage until another transistor that will be off in a second steady state when the other terminal of the switch has the higher voltage.

### Claim 4 (depends on 1)

The apparatus of claim 1 wherein the stacked switch circuit comprises circuitry to, when the stacked switch circuit is in the off state, apply a higher of the respective voltages at the terminals of the switch to a gate of a transistor in the switch's current path at the terminal of the switch that receives the higher of the respective voltages.

### Claim 5 (depends on 4)

The apparatus of claim 4 wherein the stacked switch circuit comprises circuitry to, when the stacked switch circuit is in the off state, apply the higher of the respective voltages less a second voltage to a gate of another transistor in the switch's current path that receives a lesser of the respective voltages at the terminals of the switch.

### Claim 6 (depends on 5)

The apparatus of claim 5 wherein application of the higher of the respective voltages less the second voltage to the gate of the another transistor prevents the other transistor from exceeding a maximum rating.

### Claim 7

An apparatus, comprising:
a stacked switch circuit having protection circuitry to prevent shoot through current when the switch is in an off state and respective voltages at the terminals of the switch change such that before the change one of the terminals of the switch has the higher voltage and after the change the other terminal of the switch has the higher voltage, wherein, the stacked switch circuit has first and second halves that mirror each other and the protection circuitry couples the first and second halves.

### Claim 8 (depends on 7)

The apparatus of claim 7 wherein the protection circuitry keeps at least one of the transistors in the switch's current path off during the switch.

### Claim 9 (depends on 8)

The apparatus of claim 8 wherein when the stacked switch circuit is in the off state the protection circuitry keeps off a transistor in the switch's current path that was off in a first steady state when the one terminal of the switch had the higher voltage until another transistor that will be off in a second steady state when the other terminal of the switch has the higher voltage.

### Claim 10 (depends on 7)

The apparatus of claim 7 wherein the stacked switch circuit comprises circuitry to, when the stacked switch circuit is in the off state, apply a higher of the respective voltages at the terminals of the switch to a gate of a transistor in the switch's current path at the terminal of the switch that receives the higher of the respective voltages.

### Claim 11 (depends on 10)

The apparatus of claim 10 wherein the stacked switch circuit comprises circuitry to, when the stacked switch circuit is in the off state, apply the higher of the respective voltages less a second voltage to a gate of another transistor in the switch's current path that receives a lesser of the respective voltages at the terminals of the switch.

### Claim 12 (depends on 11)

The apparatus of claim 11 wherein application of the higher of the respective voltages less the second voltage to the gate of the another transistor prevents the other transistor from exceeding a maximum rating.

### Claim 13

A computing system, comprising:
one or more processing cores;
a system memory;
a memory controller coupled to the system memory;
power supply circuitry, the power supply circuitry comprising a stacked switch circuit having protection circuitry to prevent shoot through current when the switch is in an off state and respective voltages at the terminals of the switch change such that before the change one of the terminals of the switch has the higher voltage and after the change the other terminal of the switch has the higher voltage.

### Claim 14 (depends on 13)

The apparatus of claim 13 wherein the protection circuitry keeps at least one of the transistors in the switch's current path off during the switch.

### Claim 15 (depends on 14)

The apparatus of claim 14 wherein when the stacked switch circuit is in the off state the protection circuitry keeps off a transistor in the switch's current path that was off in a first steady state when the one terminal of the switch had the higher voltage until another transistor that will be off in a second steady state when the other terminal of the switch has the higher voltage.

### Claim 16 (depends on 13)

The apparatus of claim 13 wherein the stacked switch circuit comprises circuitry to, when the stacked switch circuit is in the off state, apply a higher of the respective voltages at the terminals of the switch to a gate of a transistor in the switch's current path at the terminal of the switch that receives the higher of the respective voltages.

### Claim 17 (depends on 16)

The apparatus of claim 16 wherein the stacked switch circuit comprises circuitry to, when the stacked switch circuit is in the off state, apply the higher of the respective voltages less a second voltage to a gate of another transistor in the switch's current path that receives a lesser of the respective voltages at the terminals of the switch.

### Claim 18 (depends on 17)

The apparatus of claim 17 wherein application of the higher of the respective voltages less the second voltage to the gate of the another transistor prevents the other transistor from exceeding a maximum rating.
