# US 2019/0355889 A1 · Multilayer circuit substrate and manufacturing method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0355889 A1 - Document ID: US20190355889A1 - Status: Published application - Kind: A1 - Application number: 16/400,913 - Filed: 2019-05-01 - Published: 2019-11-21 - Earliest claimed: 2018-05-17 - Assignees: Stanley Electric Co., Ltd. - Applicants: Stanley Electric Co., Ltd. - Inventors: Akihiko HANYA - Web page: https://patentgrep.com/patent/US20190355889A1 ## CPC - H10H 20/857: Interconnections, e.g. lead-frames, bond wires or solder balls - H05K 1/097: {Inks comprising nanoparticles and specially adapted for being sintered at low temperature (H05K1/095 takes precedence)} - H05K 3/12: using {thick film techniques, e.g.} printing techniques to apply the conductive material {or similar techniques for applying conductive paste or ink patterns} - H05K 3/1283: {After-treatment of the printed patterns, e.g. sintering or curing methods} - H10H 20/01: Manufacture or treatment - H10H 20/852: Encapsulations - H10W 20/42: Vias, e.g. via plugs - H10W 20/43: Layouts of interconnections - H10H: INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS - H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract An aspect of the invention provides a multilayer circuit substrate that has a simple configuration and is thin. The multilayer circuit substrate has a stacked multiple of substrates and a wiring pattern disposed so to be sandwiched between the stacked multiple of substrates. At least one portion of the wiring pattern is configured of a conductive material wherein conductive particles are sintered. An upper face of the wiring pattern is directly joined to the substrate positioned above the wiring pattern, a lower face of the wiring pattern is directly joined to the substrate positioned below the wiring pattern, and the stacked multiple of substrates are fixed to each other by the wiring pattern. ## Claims ### Claim 1 A multilayer circuit substrate, comprising: a stacked multiple of substrates; and at least one layer of wiring pattern disposed so to be sandwiched between the stacked multiple of substrates, wherein at least one portion of the wiring pattern is configured of a conductive material wherein conductive particles are sintered, an upper face of the wiring pattern is directly joined to the substrate positioned above the wiring pattern, a lower face of the wiring pattern is directly joined to the substrate positioned below the wiring pattern, and the stacked multiple of substrates are fixed to each other by the wiring pattern. ### Claim 2 (depends on 1) The multilayer circuit substrate according to claim 1, further comprising an upper face wiring pattern, wherein the upper face wiring pattern is disposed on an upper face of a substrate positioned uppermost of the stacked multiple of substrates, at least one portion of the upper face wiring pattern is configured of a conductive material wherein conductive particles are sintered, and a lower face of the upper face wiring pattern is directly joined to the upper face of the substrate positioned uppermost. ### Claim 3 (depends on 1) The multilayer circuit substrate according to claim 1, wherein the number of the layer of the wiring pattern is two, a through hole is provided in a substrate sandwiched by two layers of the wiring pattern, a conductive portion configured of a conductive material wherein conductive particles are sintered is packed in the through hole, and the conductive portion is linked to each of the two layers of the wiring pattern. ### Claim 4 (depends on 3) The multilayer circuit substrate according to claim 3, wherein the conductive portion has a first conductive portion, which covers one aperture of the through hole so as to block the one aperture and is inserted into the through hole from the one aperture, and a second conductive portion, which covers another aperture of the through hole so as to block the other aperture and is inserted into the through hole from the other aperture, a portion of the first conductive portion inserted into the through hole is of a pillar form with a diameter smaller than a diameter of the through hole, and a portion of the second conductive portion inserted into the through hole is of a form that fills a gap between the pillar form portion of the first conductive portion and an inner wall of the through hole. ### Claim 5 (depends on 1) The multilayer circuit substrate according to claim 1, wherein the number of the substrate is three or more, two of the stacked three or more substrates are larger than another substrate sandwiched between the two substrates, the larger two substrates have regions that are directly opposed without the other substrate intervening, and an electronic part is mounted in the regions. ### Claim 6 (depends on 5) The multilayer circuit substrate according to claim 5, wherein the electronic part includes an upper face electrode on an upper face and a lower face electrode on a lower face, and the upper face electrode and the lower face electrode are connected to the wiring pattern joined to the larger two substrates. ### Claim 7 (depends on 2) The multilayer circuit substrate according to claim 2, wherein an LED die is joined to the upper face wiring pattern. ### Claim 8 (depends on 1) The multilayer circuit substrate according to claim 1, wherein the multiple of the substrate are transparent. ### Claim 9 (depends on 1) The multilayer circuit substrate according to claim 1, wherein the multiple of the substrate are made of resin. ### Claim 10 (depends on 1) The multilayer circuit substrate according to claim 1, wherein the multiple of the substrate are flexible substrates. ### Claim 11 A multilayer circuit substrate manufacturing method, comprising: a step of applying a solution in which conductive particles are dispersed in a desired form on an upper face of a first substrate, thereby forming a film; a step of mounting a second substrate on the film, and causing a lower face of the second substrate to adhere to an upper face of the film; and a step of sintering the film, thereby forming a wiring pattern whose lower face is joined directly to the first substrate and whose upper face is joined directly to the second substrate. ### Claim 12 (depends on 11) The multilayer circuit substrate manufacturing method according to claim 11, further comprising a step of concentrating the solution configuring the film applied to the first substrate, thereby forming a concentrated film, between the step of forming the film and the step of causing the lower face of the second substrate to adhere to the upper face of the film. ### Claim 13 (depends on 12) The multilayer circuit substrate manufacturing method according to claim 12, wherein the step of forming the concentrated film is a step of heating the film at a temperature lower than a fusing point of a solvent included in the solution. ### Claim 14 (depends on 11) The multilayer circuit substrate manufacturing method according to claim 11, wherein at least one of the first substrate and the second substrate is light transmitting, and the step of forming the wiring pattern is a step of sintering the conductive particles by irradiating the film with light through the light transmitting substrate.