# US 2019/0355850 A1 · FINFETS with Wrap-Around Silicide and Method Forming the Same

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- Number: US 2019/0355850 A1
- Document ID: US20190355850A1
- Status: Published application
- Kind: A1
- Application number: 16/511,493
- Filed: 2019-07-15
- Published: 2019-11-21
- Earliest claimed: 2015-02-12
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Kuo-Cheng Chiang; Ching-Wei Tsai; Chi-Wen Liu; Chih-Hao Wang; Ying-Keung Leung
- Web page: https://patentgrep.com/patent/US20190355850A1

## CPC

- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/0212: {using self-aligned silicidation}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 30/673: {characterised by the shapes, relative sizes or dispositions of the gate electrodes}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6743: {Silicon}
- H10D 30/6744: {Monocrystalline silicon}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/231: {Emitter or collector electrodes for bipolar transistors}
- H10D 84/0128: {Manufacturing their channels}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P 14/40: of conductive or resistive materials
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A device includes isolation regions extending into a semiconductor substrate, with a substrate strip between opposite portions of the isolation regions having a first width. A source/drain region has a portion overlapping the substrate strip, wherein an upper portion of the source/drain region has a second width greater than the first width. The upper portion of the source/drain region has substantially vertical sidewalls. A source/drain silicide region has inner sidewalls contacting the vertical sidewalls of the source/drain region.

## Claims

### Claim 1

A device comprising:
a bulk semiconductor substrate;
a semiconductor region over and connecting to the bulk semiconductor substrate;
isolation regions over and contacting the bulk semiconductor substrate, wherein the isolation regions are on opposite sides of the semiconductor region;
a first semiconductor strip overlapping the semiconductor region;
a first gate dielectric encircling the first semiconductor strip; and
a gate electrode comprising portions on opposite sides of the first semiconductor strip and the first gate dielectric.

### Claim 2 (depends on 1)

The device of claim 1 further comprising:
a silicon germanium oxide region overlapping the semiconductor region, wherein the silicon germanium oxide region is between the first semiconductor strip and the semiconductor region.

### Claim 3 (depends on 2)

The device of claim 2, wherein the silicon germanium oxide region physically contacts the first gate dielectric.

### Claim 4 (depends on 2)

The device of claim 2, wherein the silicon germanium oxide region is separated from the first gate dielectric by a portion of the gate electrode.

### Claim 5 (depends on 1)

The device of claim 1 further comprising:
a second semiconductor strip overlapping the first semiconductor strip; and
a second gate dielectric encircling the second semiconductor strip, wherein the first gate dielectric contacts the second gate dielectric.

### Claim 6 (depends on 5)

The device of claim 5, wherein each of the first gate dielectric and the second gate dielectric comprises:
a silicon oxide layer encircling the respective one of the first and the second semiconductor strips, and the silicon oxide layer encircling the first semiconductor strip is in contact with the silicon oxide layer encircling the second semiconductor strip; and
a high-k dielectric layer comprising portions on opposite sides of, and contacting, the silicon oxide layer.

### Claim 7 (depends on 1)

The device of claim 1, wherein the first semiconductor strip has a round cross-sectional shape.

### Claim 8

A device comprising:
a first silicon strip;
a first gate dielectric encircling the first silicon strip;
a silicon germanium oxide layer overlapped by the first silicon strip and the first gate dielectric;
a semiconductor region overlapped by the silicon germanium oxide layer;
a gate electrode on the first gate dielectric; and
source and drain regions connected to opposite ends of the first silicon strip.

### Claim 9 (depends on 8)

The device of claim 8, wherein the first silicon strip has a lengthwise direction parallel to a major top surface of the silicon germanium oxide layer.

### Claim 10 (depends on 8)

The device of claim 8 further comprising shallow trench isolation regions on opposite sides of, and contacting sidewalls of, the silicon germanium oxide layer and the semiconductor region.

### Claim 11 (depends on 10)

The device of claim 10, wherein the silicon germanium oxide layer has a first portion lower than top surfaces of the shallow trench isolation regions, and a second portion higher than the top surfaces of the shallow trench isolation regions.

### Claim 12 (depends on 8)

The device of claim 8 further comprising:
a second silicon strip overlapping the first silicon strip; and
a second gate dielectric encircling the second silicon strip, wherein the first gate dielectric is joined to the second gate dielectric.

### Claim 13 (depends on 12)

The device of claim 12, wherein each of the first gate dielectric and the second gate dielectric comprises:
a silicon oxide layer, wherein the silicon oxide layer of the first gate dielectric and the silicon oxide layer of the second gate dielectric are joined to each other; and
a high-k dielectric layer, wherein the high-k dielectric layer of the first gate dielectric and the high-k dielectric layer of the second gate dielectric are joined to each other.

### Claim 14 (depends on 8)

The device of claim 8, wherein the silicon germanium oxide layer comprises:
a lower portion; and
an upper portion narrower than the lower portion.

### Claim 15 (depends on 8)

The device of claim 8, wherein the first silicon strip is intrinsic.

### Claim 16

A device comprising:
a plurality of semiconductor strips, with higher ones of the plurality of semiconductor strips overlapping lower ones of the plurality of semiconductor strips;
a plurality of gate dielectrics, each encircling one of the plurality of semiconductor strips, wherein the plurality of gate dielectrics are joined together;
a gate electrode contacting the plurality of gate dielectrics; and
a source/drain region connected to ends of the plurality of semiconductor strips.

### Claim 17 (depends on 16)

The device of claim 16 further comprising a first isolation region and a second isolation region on opposite sides of, and lower than, the plurality of semiconductor strips.

### Claim 18 (depends on 17)

The device of claim 17, wherein the source/drain region extends into a region between the first isolation region and the second isolation region, and a bottom of the source/drain region is lower than top surfaces of the first isolation region and the second isolation region.

### Claim 19 (depends on 16)

The device of claim 16, wherein the plurality of gate dielectrics comprise a plurality of oxide layers, each encircling one of the plurality of semiconductor strips, and a plurality of high-k dielectric layers, each on opposite sides of one of the plurality of oxide layers, wherein the plurality of oxide layers are joined to form a continuous oxide region, and the plurality of high-k dielectric layers are joined to form a continuous high-k dielectric region.

### Claim 20 (depends on 16)

The device of claim 16 further comprising a silicon germanium oxide layer overlapped by the plurality of semiconductor strips.