# US 2019/0355848 A1 · Semiconductor device and method of manufacturing the same

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- Number: US 2019/0355848 A1
- Document ID: US20190355848A1
- Status: Published application
- Kind: A1
- Application number: 16/531,793
- Filed: 2019-08-05
- Published: 2019-11-21
- Earliest claimed: 2017-01-13
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Jong Su Kim
- Web page: https://patentgrep.com/patent/US20190355848A1

## CPC

- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/292: {Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512)}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10W 20/0698: {Local interconnections}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 84/0195: {the components including vertical IGFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10P 50/283: {by chemical means}
- H10P 76/2043: {using an anti-reflective coating}
- H10P 95/062: {involving a dielectric removal step}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a substrate, and a first source/drain region formed on the substrate. The semiconductor device further includes a channel formed on the first source/drain region, and a second source/drain region formed on the channel. The semiconductor device also includes a gate electrode formed on an external surface of the channel, and a metal pad formed on the substrate. The height of an upper surface of the metal pad is the same as the length of an upper surface of the gate electrode.

## Claims

### Claim 1

A method for manufacturing a semiconductor device, the method comprising:
forming a first source/drain region on a substrate;
forming a channel on the first source/drain region;
forming a second source/drain region on the channel;
forming a gate electrode on an outer surface of the channel; and
forming a metal pad on the substrate;
wherein a height of an upper surface of the metal pad is the same as a height of an upper surface of the gate electrode.

### Claim 2 (depends on 1)

The method of claim 1, wherein forming the gate electrode and forming the metal pad occur simultaneously.

### Claim 3 (depends on 1)

The method of claim 1, wherein the gate electrode and the metal pad include the same material selected from tungsten (W), cobalt (Co), copper (Cu), tantalum (Ta), titanium (Ti), ruthenium (Ru), aluminum (Al), metal carbides, or metal nitrides.

### Claim 4 (depends on 1)

The method of claim 1, wherein forming the metal pad on the substrate comprises forming the metal pad on a silicide layer formed on the substrate.

### Claim 5 (depends on 4)

The method of claim 4, wherein a height of an upper surface of the silicide layer is the same as a height of an upper surface of a bottom spacer.

### Claim 6 (depends on 1)

The method of claim 1, further comprising forming a gate dielectric layer between the channel and the gate electrode.

### Claim 7 (depends on 1)

The method of claim 1, further comprising:
forming a first aperture coupled to the metal pad; and
forming a second aperture coupled to the gate electrode,
wherein a longitudinal length of the first aperture is substantially the same as a longitudinal height of the second aperture.

### Claim 8 (depends on 7)

The method of claim 7, wherein the first and second apertures are formed simultaneously,

### Claim 9

A method for manufacturing a semiconductor device, the method comprising:
forming a first spacer layer, a silicide layer, and a stack comprising a first insulating layer and a vertical channel on a substrate;
forming a gate metal layer on the first spacer layer, the silicide layer, and the stack;
forming a second spacer layer over the gate metal layer and the stack;
forming an organic planarization layer (OPL) over the second spacer layer;
removing a portion of the OPL, the second spacer layer, and the gate metal layer to expose a portion of the first spacer layer;
removing remaining portion of the OPL;
forming a third spacer layer over the second spacer layer, the gate metal layer, and the stack;
forming a second insulating layer over the second spacer layer;
removing the first insulating layer of the stack;
forming an upper source/drain region on the vertical channel;
forming a fourth spacer layer on a second source/drain region;
forming a third insulating layer on the second source/drain region;
forming a first and second apertures on the silicide layer and the first spacer layer simultaneously; and
forming a third aperture on the second source/drain region;
wherein a height of the gate metal layer on the silicide layer is the same as a height of the gate metal layer on the first spacer layer.

### Claim 10 (depends on 9)

The method of claim 9, wherein the silicide layer is overlapped with the first aperture when viewed from a direction perpendicular to a surface of the substrate.

### Claim 11 (depends on 9)

The method of claim 9, wherein the gate metal layer includes tungsten (W), cobalt (Co), copper (Cu), tantalum (Ta), titanium (Ti), ruthenium (Ru), aluminum (Al), metal carbides, or metal nitrides.

### Claim 12 (depends on 9)

The method of claim 9, wherein the first spacer layer includes titanium nitride (TiN).

### Claim 13 (depends on 9)

The method of claim 9, further comprising forming a gate dielectric layer between the vertical channel and the gate metal layer.

### Claim 14 (depends on 9)

The method of claim 9, further comprising forming a lower source/drain region on the substrate.

### Claim 15

A method of constructing an integrated circuit, the method comprising:
forming a silicide layer, a first spacer layer, and a stack including a plurality of layers on a substrate, respectively, with the stack surrounded by the first spacer layer, and with the silicide layer and the first spacer layer positioned right next to each other;
forming a metal layer on the first spacer layer and the silicide layer;
forming a photoresist layer on the metal layer;
patterning the photoresist layer;
removing a first portion of the metal layer formed on a first portion of the first spacer layer that is positioned between the silicide layer and the stack;
forming a second portion of the metal layer on the silicide layer and a third portion of the metal layer on a second portion of the first spacer layer, with a thickness of the second portion of the metal layer being the same as the thickness of the third portion; and
manufacturing the integrated circuit including the second and third portions of the metal layers.