# US 2019/0355846 A1 · Trench gate mosfet and method of manufacturing the same

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- Number: US 2019/0355846 A1
- Document ID: US20190355846A1
- Status: Published application
- Kind: A1
- Application number: 16/412,427
- Filed: 2019-05-15
- Published: 2019-11-21
- Earliest claimed: 2018-05-16
- Assignees: uPI Semiconductor Corp.
- Applicants: uPI Semiconductor Corp.
- Inventors: Nobuyuki Shirai; Chun-Hsu Chang; Ming-Hung Chou
- Web page: https://patentgrep.com/patent/US20190355846A1

## CPC

- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10P 14/61: using masks
- H10D 30/0293: {using formation of insulating sidewall spacers}
- H10D 30/0297: {using recessing of the gate electrodes, e.g. to form trench gate electrodes}
- H10D 64/117: {Recessed field plates, e.g. trench field plates or buried field plates}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10P 76/405: {characterised by their composition, e.g. multilayer masks}
- H10P 76/4085: {characterised by the processes involved to create the masks}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Provided is a method of forming a trench gate MOSFET. A hard mask layer is formed on a substrate. The substrate is partially removed by using the hard mask layer as a mask, so as to form a trench in the substrate. A first insulating layer and a first conductive layer are formed in the lower portion of the trench. A sacrificial layer is formed on the side surface of the upper portion of the trench, and the sacrificial layer is connected to the hard mask layer. An interlayer insulating layer is formed on the first conductive layer by a thermal oxidation process when the sacrificial layer and the hard mask layer are present. A second insulating layer and a second conductive layer are formed in the upper portion of the trench. A trench gate MOSFET is further provided.

## Claims

### Claim 1

A method of manufacturing a trench gate MOSFET, comprising:
forming a hard mask layer on a substrate;
partially removing the substrate by using the hard mask layer as a mask, so as to form a trench in the substrate;
forming a first insulating layer and a first conductive layer in a lower portion of the trench;
forming a sacrificial layer on a sidewall of an upper portion of the trench, wherein the sacrificial layer is connected to the hard mask layer;
forming an interlayer insulating layer on the first conductive layer by a thermal oxidation process when the sacrificial layer and the hard mask layer are present; and
forming a second insulating layer and a second conductive layer in the upper portion of the trench.

### Claim 2 (depends on 1)

The method of claim 1, further comprising removing the sacrificial layer and the hard mask layer after forming the interlayer insulating layer.

### Claim 3 (depends on 1)

The method of claim 1, further comprising removing the sacrificial layer and a portion of the hard mask layer after forming the interlayer insulating layer.

### Claim 4 (depends on 3)

The method of claim 3, wherein a material of the remaining hard mask layer comprises silicon nitride or silicon oxynitride after removing the portion of the hard mask layer.

### Claim 5 (depends on 1)

The method of claim 1, wherein the hard mask layer is a multi-layer composite structure, and a material of the sacrificial layer is the same as a material of one layer of the hard mask layer.

### Claim 6 (depends on 1)

The method of claim 1, wherein after forming the interlayer insulating layer, the trench has a width W1 at a surface of the substrate and a width W2 at a depth of 100-150 nm from the surface of the substrate, and a ratio of W1 to W2 is greater than 1 and less than 1.08.

### Claim 7

A trench gate MOSFET, comprising:
a substrate, having a trench therein;
a first conductive layer, disposed in a lower portion of the trench;
a first insulating layer, disposed between the first conductive layer and the substrate;
a second conductive layer, disposed in the trench and located on the first conductive layer;
a second insulating layer, disposed between the second conductive layer and the substrate; and
an interlayer insulating layer, disposed between the first conductive layer and the second conductive layer, wherein the interlayer insulating layer is dielectric oxide,
wherein the trench has a width W1 at a surface of the substrate and a width W2 at a depth of 100-150 nm from the surface of the substrate, and a ratio of W1 to W2 is greater than 1 and less than 1.08.

### Claim 8 (depends on 7)

The trench gate MOSFET of claim 7, further comprising a nitrogen-containing hard mask layer disposed on the substrate beside the trench.

### Claim 9 (depends on 7)

The trench gate MOSFET of claim 7, wherein a top surface of a central portion of the interlayer insulating layer is higher than a top surface of an edge portion of the interlayer insulating layer.

### Claim 10 (depends on 7)

The trench gate MOSFET of claim 7, wherein a nitrogen-containing hard mask layer is present on the surface of the substrate beside the trench when the interlayer insulating layer is formed by a thermal oxidation process.