# US 2019/0355843 A1 · Group iii-nitride integrated front-end circuit

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- Number: US 2019/0355843 A1
- Document ID: US20190355843A1
- Status: Published application
- Kind: A1
- Application number: 16/475,220
- Filed: 2017-02-02
- Published: 2019-11-21
- Earliest claimed: 2017-02-02
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Han Wui THEN; Sansaptak DASGUPTA; Marko RADOSAVLJEVIC
- Web page: https://patentgrep.com/patent/US20190355843A1

## CPC

- H04B 1/04: Circuits
- H10D 30/475: {having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs}
- H04B 1/16: Circuits
- H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10D 62/117: {Shapes of semiconductor bodies}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H04B: TRANSMISSION
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An apparatus, an integrated circuit die, and a method of fabricating a group III-nitride (III-N) integrated RF front-end circuit are disclosed. The apparatus includes a III-N integrated radio frequency (RF) front-end circuit that includes a semiconductor substrate, a plurality of functional blocks, each of the plurality of functional blocks comprising a III-N structure on the semiconductor substrate. The III-N integrated RF front-end circuit is to be coupled to an antenna.

## Claims

### Claim 1

An apparatus comprising:
a group III-nitride (III-N) integrated radio frequency (RF) front-end circuit comprising:
a semiconductor substrate;
a plurality of functional blocks, each of the plurality of functional blocks comprising a III-N structure on the semiconductor substrate, wherein the III-N integrated RF front-end circuit is to be coupled to an antenna.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the plurality of functional blocks comprises:
a power amplifier (PA) comprising a first III-N structure on the semiconductor substrate; and
a low-noise amplifier (LNA) comprising a second III-N structure on the semiconductor substrate.

### Claim 3 (depends on 2)

The apparatus of claim 2, wherein the plurality of functional blocks further comprises:
a voltage regulator (VR) comprising a third III-N structure on the semiconductor substrate; and
an n-type metal-oxide-semiconductor logic (NMOS) comprising a fourth III-N structure on the semiconductor substrate.

### Claim 4 (depends on 3)

The apparatus of claim 3, wherein the plurality of functional blocks further comprises a switch comprising a fifth III-N structure on the semiconductor substrate.

### Claim 5 (depends on 2)

The apparatus of claim 2, wherein the plurality of functional blocks is coupled to a second plurality of functional blocks, the second plurality of functional blocks comprising:
a voltage regulator (VR) comprising a third III-N structure on a second semiconductor substrate; and
an n-type metal-oxide-semiconductor logic (NMOS) comprising a fourth III-N structure on the second semiconductor substrate.

### Claim 6 (depends on 5)

The apparatus of claim 5, wherein the plurality of functional blocks is coupled to a switch, the switch comprising a fifth III-N structure on a third semiconductor substrate.

### Claim 7 (depends on 1)

The apparatus of claim 1, wherein the III-N structure is a gallium nitride (GaN) structure.

### Claim 8 (depends on 1)

The apparatus of claim 1, wherein a wireless communication device comprises:
the III-N integrated RF front-end circuit;
the antenna;
filters coupled between the antenna and the III-N integrated RF front-end circuit; and
silicon complementary metal-oxide-semiconductor (Si CMOS) logic coupled to the III-N integrated RF front-end circuit.

### Claim 9 (depends on 1)

The apparatus of claim 1, wherein each of the plurality of functional blocks comprises:
a gallium nitride (GaN) structure above the semiconductor substrate;
a plurality of source terminals on the GaN structure;
a plurality of drain terminals on the GaN structure; and
a plurality of gate terminals above the GaN structure, wherein each of the plurality of gate terminals is between a source terminal of the plurality of source terminals and a drain terminal of the plurality of drain terminals.

### Claim 10 (depends on 9)

The apparatus of claim 9, wherein each GaN structure is grown directly on the semiconductor substrate, wherein the GaN structures are separated by one or more shallow trench isolations (STI).

### Claim 11 (depends on 1)

The apparatus of claim 1, wherein the semiconductor substrate comprises silicon.

### Claim 12

An integrated circuit die comprising:
a semiconductor substrate;
a group III-nitride (III-N) structure above the semiconductor substrate;
a source terminal and a drain terminal on the III-N structure;
a polarization layer above the III-N structure between the source terminal and the drain terminal; and
a gate terminal above the polarization layer.

### Claim 13 (depends on 12)

The integrated circuit die of claim 12 further comprising:
a first trench contact on the drain terminal;
a second trench contact on the source terminal;
an aluminum nitride (AlN) layer on the III-N structure between the source terminal and the drain terminal, wherein the polarization layer is on the AlN layer; and
a high-k dielectric layer, wherein:
the gate terminal is a t-shape and comprises a lower portion and an upper portion;
a first portion of the high-k dielectric layer is on the lower surface of the lower portion of the gate terminal;
a second portion of the high-k dielectric layer is on sidewalls of the lower portion of the gate terminal; and
the polarization layer is between the AlN layer and the first portion of the high-k dielectric layer.

### Claim 14 (depends on 13)

The integrated circuit die of claim 13 further comprising:
a first shallow trench isolation (STI) and a second STI on the semiconductor substrate; and
a first layer of III-N on the semiconductor substrate between the first STI and the second STI, wherein the III-N structure is on the first layer of III-N.

### Claim 15 (depends on 14)

The integrated circuit die of claim 14 further comprising:
a first spacer on the polarization layer and the second portion of the high-k dielectric layer;
a second spacer on the first spacer and on the second portion of the high-k dielectric layer;
a first inter-layer dielectric (ILD) on the first STI, the second STI, the III-N structure, the drain terminal, the source terminal, the first trench contact, first spacer, the second spacer, a lower surface of the upper portion of the gate terminal, and the second trench contact; and
a second ILD on the first ILD, the first trench contact, sidewalls of the upper portion of the gate terminal, and the second trench contact.

### Claim 16 (depends on 15)

The integrated circuit die of claim 15, wherein:
the semiconductor substrate is a silicon (Si) (111) structure;
the first STI and the second STI are a first oxide;
the III-N structure and first layer of III-N are gallium nitride (GaN);
the polarization layer is indium aluminum nitride (InAlN);
the first spacer is a silicon oxide;
the second spacer is a silicon nitride; and
the first ILD is a second oxide.

### Claim 17 (depends on 12)

The integrated circuit die of claim 12, wherein:
the source terminal comprises indium gallium nitride (InGaN) and n-type doping; and
the drain terminal comprises InGaN and n-type doping.

### Claim 18 (depends on 12)

The integrated circuit die of claim 12, wherein the III-N structure is grown directly on the semiconductor substrate in a reactor.

### Claim 19

A method of fabricating a group III-nitride (III-N) integrated radio frequency (RF) front-end circuit, the method comprising:
forming a III-N structure above a semiconductor substrate;
forming a polarization layer above the III-N structure;
forming a source terminal and a drain terminal on the III-N structure, wherein the polarization layer is between the source terminal and the drain terminal; and
forming a gate terminal above the polarization layer.

### Claim 20 (depends on 19)

The method of claim 19 further comprising:
forming a first trench contact on the drain terminal;
forming a second trench contact on the source terminal;
forming an aluminum nitride (AlN) layer on the III-N structure between the source terminal and the drain terminal, wherein the polarization layer is formed on the AlN layer; and
forming a high-k dielectric layer, wherein:
the gate terminal is a t-shape and comprises a lower portion and an upper portion;
a first portion of the high-k dielectric layer is formed on the lower surface of the lower portion of the gate terminal;
a second portion of the high-k dielectric layer is formed on sidewalls of the lower portion of the gate terminal; and
the polarization layer is between the AlN layer and the first portion of the high-k dielectric layer.

### Claim 21 (depends on 20)

The method of claim 20 further comprising:
forming a first shallow trench isolation (STI) and a second STI on the semiconductor substrate; and
forming a first layer of III-N on the semiconductor substrate between the first STI and the second STI, wherein the III-N structure is formed on the first layer of III-N.

### Claim 22 (depends on 21)

The method of claim 21 further comprising:
disposing a first spacer on the polarization layer and the second portion of the high-k dielectric layer;
disposing a second spacer on the first spacer and on the second portion of the high-k dielectric layer;
disposing a first inter-layer dielectric (ILD) on the first STI, the second STI, the III-N structure, the drain terminal, the source terminal, the first trench contact, first spacer, the second spacer, a lower surface of the upper portion of the gate terminal, and the second trench contact; and
disposing a second ILD on the first ILD, the first trench contact, sidewalls of the upper portion of the gate terminal, and the second trench contact.

### Claim 23 (depends on 22)

The method of claim 22, wherein:
the semiconductor substrate is a silicon (Si) (111) structure;
the first STI and the second STI are a first oxide;
the III-N structure and first layer of III-N are gallium nitride (GaN);
the polarization layer is indium aluminum nitride (InAlN);
the first spacer is a silicon oxide;
the second spacer is a silicon nitride;
the first ILD is a second oxide;
the source terminal comprises indium gallium nitride (InGaN) and n-type doping; and
the drain terminal comprises InGaN and n-type doping.

### Claim 24 (depends on 19)

The method of claim 19, wherein the III-N structure is grown directly on the semiconductor substrate in a reactor.