# US 2019/0355840 A1 · Semiconductor device and method for manufacturing semicondcutor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0355840 A1 - Document ID: US20190355840A1 - Status: Published application - Kind: A1 - Application number: 16/317,852 - Filed: 2017-07-11 - Published: 2019-11-21 - Earliest claimed: 2016-07-15 - Assignees: Rohm Co., Ltd. - Applicants: Rohm Co., Ltd. - Inventors: Seigo MORI; Masatoshi AKETA - Web page: https://patentgrep.com/patent/US20190355840A1 ## CPC - H10D 12/441: {Vertical IGBTs} - H10D 62/106: {having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions} - H10D 12/00: Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT] - H10D 12/031: {of IGBTs} - H10D 12/032: {of vertical IGBTs} - H10D 12/481: {having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs} - H10D 30/0291: {of vertical DMOS [VDMOS] FETs} - H10D 30/0297: {using recessing of the gate electrodes, e.g. to form trench gate electrodes} - H10D 30/66: Vertical DMOS [VDMOS] FETs - H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors} - H10D 62/107: {Buried supplementary regions, e.g. buried guard rings (multi-RESURF H10D62/111)} - H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs} - H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)} - H10D 62/8325: {Silicon carbide} - H10D 64/011: {of electrodes ohmically coupled to a semiconductor} - H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)} - H10D 84/00: Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers - H10D 84/0109: {the at least one component covered by H10D12/00 or H10D30/00 being a MOS device} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 84/144: {in antiparallel diode configurations} - H10P 14/3408: {Silicon carbide} - H10P 30/2042: {into crystalline silicon carbide} - H10P 30/21: {of electrically active species} - H10P 30/28: characterised by an annealing step, e.g. for activation of dopants - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor device includes a first conductivity type first semiconductor layer, a second conductivity type second semiconductor layer on the first semiconductor layer, an MIS transistor structure defined in a surface portion of the second semiconductor layer, a trench defined selectively in the first semiconductor layer, and a first electrode defined on a back surface of the first semiconductor layer such that the first electrode enters the trench, in which the second semiconductor layer has a second conductivity type region in a manner extending across a first portion exposed at the bottom portion of the trench and a second portion in contact with the first conductivity type layer, and the first electrode is in Ohmic contact with the second conductivity type region at least at the bottom portion of the trench and in Ohmic contact with the first semiconductor layer, and the second conductivity type region has a carrier lifetime of equal to or longer than 0.1 μs. ## Claims ### Claim at position 1 1-24. (canceled) ### Claim 25 A semiconductor device comprising: a first conductivity type first semiconductor layer; a second conductivity type second semiconductor layer on the first semiconductor layer; an MIS transistor structure defined in a surface portion on the side of the second semiconductor layer opposite to the first semiconductor layer; a trench defined selectively in the first semiconductor layer and having a bottom portion reaching the second semiconductor layer; and a first electrode defined on a back surface of the first semiconductor layer such that the first electrode enters the trench, wherein the second semiconductor layer has a second conductivity type region in a manner extending across a first portion exposed at the bottom portion of the trench and a second portion in contact with the first conductivity type layer, and the first electrode is in Ohmic contact with the second conductivity type region at least at the bottom portion of the trench and in Ohmic contact with the first semiconductor layer, and the second conductivity type region has a carrier lifetime of equal to or longer than 0.1 μs. ### Claim 26 (depends on 25) The semiconductor device according to claim 25, wherein the trench is defined to have a depth greater than a thickness of the first semiconductor layer such that a recessed portion is defined in the second semiconductor layer. ### Claim 27 (depends on 25) The semiconductor device according to claim 25, wherein the second semiconductor layer has a flat back surface continuing between the first portion and the second portion. ### Claim 28 (depends on 25) The semiconductor device according to claim 25, wherein a side portion of the trench is constituted only by the first semiconductor layer. ### Claim 29 (depends on 25) The semiconductor device according to claim 25, wherein the MIS transistor structure includes a first conductivity type body region, a second conductivity type source region defined in a surface portion of the body region, a gate insulating film being contact with the body region, and a gate electrode opposed to the body region with the gate insulating film therebetween, and wherein the second conductivity type region includes a drift region defined nearer the first semiconductor layer with respect to the body region and in contact with the body region. ### Claim 30 (depends on 25) The semiconductor device according to claim 25, further comprising a surface terminal structure defined in an outer peripheral region around an active region in which the MIS transistor structure is defined. ### Claim 31 (depends on 29) The semiconductor device according to claim 29, wherein the second conductivity type region includes a field stop region defined between the drift region and the first semiconductor layer and having a concentration higher than that of the drift region. ### Claim 32 (depends on 25) The semiconductor device according to claim 25, wherein the trench sections the first semiconductor layer into a plurality of first conductivity type units having at least a minimum width Wmin, and wherein the width Wmin of the first conductivity type units is equal to or greater than the width of one cell in the MIS transistor structure. ### Claim 33 (depends on 25) The semiconductor device according to claim 25, wherein the trench sections the first semiconductor layer into a plurality of first conductivity type units having at least a minimum width Wmin, and wherein the width Wmin of the first conductivity type units is equal to or greater than twice a thickness of the second semiconductor layer. ### Claim 34 (depends on 25) The semiconductor device according to claim 25, wherein the trench sections the first semiconductor layer into a plurality of first conductivity type units, and wherein the plurality of first conductivity type units are arranged in a striped manner in plan view. ### Claim 35 (depends on 25) The semiconductor device according to claim 25, wherein the trench sections the first semiconductor layer into a plurality of first conductivity type units, and wherein the plurality of first conductivity type units are each defined in a polygonal shape and arranged discretely in plan view. ### Claim 36 (depends on 25) The semiconductor device according to claim 25, wherein the trench sections the first semiconductor layer into a plurality of first conductivity type units, and wherein the plurality of first conductivity type units are each defined in a circular shape and arranged discretely in plan view. ### Claim 37 (depends on 25) The semiconductor device according to claim 25, wherein the first electrode is defined in a manner following the back surface of the first semiconductor layer and an interior surface of the trench. ### Claim 38 (depends on 25) The semiconductor device according to claim 25, wherein the first electrode is buried in the trench and further defined on the back surface of the first semiconductor layer. ### Claim 39 (depends on 25) The semiconductor device according to claim 25, wherein the first semiconductor layer has a thickness of 5 μm to 350 μm. ### Claim 40 (depends on 25) The semiconductor device according to claim 25, further comprising a second electrode defined on the second semiconductor layer and connected electrically to the MIS transistor structure. ### Claim 41 (depends on 25) The semiconductor device according to claim 25, wherein the first semiconductor layer and the second semiconductor layer are made of wide bandgap semiconductor. ### Claim 42 A semiconductor device manufacturing method comprising the steps of: defining a second conductivity type second semiconductor layer on one of the surfaces of a first conductivity type first semiconductor layer; defining an MIS transistor structure in a surface portion on the side of the second semiconductor layer opposite to the first semiconductor layer; selectively etching the other surface of the first semiconductor layer opposite to the second semiconductor layer to define a trench having a bottom portion reaching the second semiconductor layer; and defining a first electrode to be in Ohmic contact with the second conductivity type region of the second semiconductor layer at least at the bottom portion of the trench and in Ohmic contact with the first semiconductor layer on the other surface of the first semiconductor layer so as to enter the trench. ### Claim 43 (depends on 42) The semiconductor device manufacturing method according to claim 42, wherein the step of defining the second semiconductor layer comprises the step of epitaxially growing the second semiconductor layer on the first semiconductor layer that is prepared as a substrate. ### Claim 44 (depends on 42) The semiconductor device manufacturing method according to claim 42, wherein the step of defining the second semiconductor layer comprises the steps of: epitaxially growing the first semiconductor layer on a second conductivity type substrate; epitaxially growing the second semiconductor layer on the first semiconductor layer; and removing the second conductivity type substrate. ### Claim 45 (depends on 42) The semiconductor device manufacturing method according to claim 42, further comprising the step of thinning the first semiconductor layer from the other surface before the step of defining the trench. ### Claim 46 (depends on 45) The semiconductor device manufacturing method according to claim 45, wherein the step of thinning the first semiconductor layer comprises the step of polishing and finishing the other surface of the first semiconductor layer. ### Claim 47 (depends on 42) The semiconductor device manufacturing method according to claim 42, wherein the step of defining the first electrode comprises the step of laser-annealing and sintering the first electrode defined on the other surface of the first semiconductor layer. ### Claim 48 A semiconductor device comprising: a first conductivity type first semiconductor layer formed by epitaxial growth; a second conductivity type second semiconductor layer formed on the first semiconductor layer by epitaxial growth; an MIS transistor structure defined in a surface portion on the side of the second semiconductor layer opposite to the first semiconductor layer; a trench defined selectively in the first semiconductor layer and having a bottom portion reaching the second semiconductor layer; and a first electrode defined on a back surface of the first semiconductor layer such that the first electrode enters the trench, wherein the second semiconductor layer has a second conductivity type region in a manner extending across a first portion exposed at the bottom portion of the trench and a second portion in contact with the first conductivity type layer, and the first electrode is in Ohmic contact with the second conductivity type region at least at the bottom portion of the trench and in Ohmic contact with the first semiconductor layer.