# US 2019/0355836 A1 · Manufacturing method for amorphous silicon tft substrate

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- Number: US 2019/0355836 A1
- Document ID: US20190355836A1
- Status: Published application
- Kind: A1
- Application number: 16/313,045
- Filed: 2018-09-27
- Published: 2019-11-21
- Earliest claimed: 2018-05-21
- Assignees: Wuhan China Star Optoelectronics Technology Co., Ltd.
- Applicants: Wuhan China Star Optoelectronics Technology Co., Ltd.
- Inventors: Guanghui Liu
- Web page: https://patentgrep.com/patent/US20190355836A1

## CPC

- H10D 30/0314: {of lateral top-gate TFTs comprising only a single gate}
- H10D 30/0321: {comprising silicon, e.g. amorphous silicon or polysilicon}
- H10D 30/6731: {Top-gate only TFTs}
- H10D 30/6746: {Amorphous silicon}
- H10D 86/0231: {using masks, e.g. half-tone masks}
- H10P 14/3442: {N-type}
- H10P 14/43: Chemical deposition, e.g. chemical vapour deposition [CVD]
- H10P 14/44: Physical vapour deposition [PVD]
- H10P 14/6334: {using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition (deposition by physical ablation of a target H10P14/6329)}
- H10P 50/691: {for Group IV materials or Group III-V materials}
- H10P 50/71: {using masks for conductive or resistive materials}
- H10P 70/27: {during, before or after processing of conductive materials, e.g. polysilicon or amorphous silicon layers}
- H10W 20/0698: {Local interconnections}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A manufacturing method for amorphous silicon TFT substrate is provided. A first photoresist layer having three thicknesses is formed through a first exposure process. Through three etching processes and two ashing treatments, patterning four layers of amorphous silicon layer, N-type doped amorphous silicon layer, first transparent conductive layer, and the source drain metal layer is completed by the first photoresist layer. Patterning of passivation layer is then performed via a second exposure process. Finally, a second photoresist layer having a photoresist pattern with two thicknesses is formed through a third exposure process. Patterning the two layers of the second transparent conductive layer and the gate metal layer by the second photoresist layer by two etching processes and one ashing process. The present invention further saves a mask process compared with the existing 4mask process, realizing a 3mask fabrication process of the amorphous silicon TFT substrate.

## Claims

### Claim 1

A manufacturing method for amorphous silicon TFT substrate, comprising steps of:
step S1, providing a base substrate, and sequentially depositing an amorphous silicon layer, an N-type doped amorphous silicon layer, a first transparent conductive layer, and a source drain metal layer on the base substrate;
step S2, coating a photoresist material on the source drain metal layer and performing a first mask process to form a first photoresist layer, wherein the first photoresist layer has a first photoresist pattern, a second photoresist pattern, and a third photoresist pattern which are sequentially increased in thickness;
Step S3, performing a first etching process by using the first photoresist layer as a shielding layer to remove the amorphous silicon layer, the N-type doped amorphous silicon layer, and the first transparent conductive layer and the source drain metal layer that are not covered by the first photoresist layer, wherein an amorphous silicon active layer is obtained from the amorphous silicon layer corresponding to an underside of the first photoresist pattern and the second photoresist pattern, and a pixel electrode is obtained from the first transparent conductive layer corresponding to an underside of the third photoresist pattern;
Step S4, performing a first ashing treatment on the first photoresist layer, thinning the second photoresist pattern and the third photoresist pattern, and removing the first photoresist pattern;
Step S5, performing a second etching process using the first photoresist layer as a shielding layer to remove the N-type doped amorphous silicon layer, the first transparent conductive layer, and the source drain metal layer that are not covered by the first photoresist layer, wherein a source electrode and a drain electrode are obtained from the source drain metal layer located above two ends of the amorphous silicon active layer and corresponding to an underside of the second photoresist pattern, and a source-drain contact region is obtained from the N-type doped amorphous silicon layer corresponding to an underside of the source electrode and the drain electrode;
Step S6, performing a second ashing treatment to the first photoresist layer, thinning the third photoresist pattern and removing the second photoresist pattern;
Step S7, performing a third etching process by using the first photoresist layer as a shielding layer, and removing the source drain metal layer corresponding to an upside of the pixel electrode to expose the pixel electrode, and peeling off a remaining portion of the first photoresist layer;
Step S8, depositing a passivation layer that covers the amorphous silicon active layer, the source electrode, the drain electrode, and the pixel electrode on the base substrate, through a second mask process, forming a first via and a second via respectively corresponding to the drain electrode and the pixel electrode on the passivation layer;
Step S9, sequentially depositing a second transparent conductive layer and a gate metal layer on the passivation layer, coating a photoresist material on the source drain metal layer and performing a third mask process to form a second photoresist layer, wherein the second photoresist layer has a fourth photoresist pattern and a fifth photoresist pattern which are sequentially increased in thickness;
Step S10, performing a first etching process using the second photoresist layer as a shielding layer to remove the second transparent conductive layer and the gate metal layer which are not covered by the second photoresist layer, wherein corresponding to an underside of the fourth photoresist pattern, a gate electrode and a metal common electrode line separated from the gate electrode which are corresponding to an upside of the amorphous silicon active layer are obtained; corresponding to an underside of the fifth photoresist pattern, a conductive connection block and a transparent common electrode line separated from the conductive connection block are obtained from the second transparent conductive layer; wherein the conductive connection block is contacted with the drain electrode and the pixel electrode respectively through the first via and the second via in order to electrically conduct the drain electrode and the pixel electrode;
Step S11, performing a first ashing treatment to the second photoresist layer, thinning the fifth photoresist pattern and removing the fourth photoresist pattern; and
Step S12, performing a second etching process using the second photoresist layer as a shielding layer to remove the gate metal layer corresponding to an upside of the conductive connection block and the transparent common electrode line, and peeling off a remaining portion of the second photoresist layer.

### Claim 2 (depends on 1)

The manufacturing method for amorphous silicon TFT substrate according to claim 1, wherein in the step S2, the first mask process is performed by a Gray Tone Mask.

### Claim 3 (depends on 1)

The manufacturing method for amorphous silicon TFT substrate according to claim 1, wherein in the step S9, the third mask process is performed by a Gray Tone Mask or a Half Tone Mask.

### Claim 4 (depends on 2)

The manufacturing method for amorphous silicon TFT substrate according to claim 2, wherein in the step S2, the coated photoresist material is a positive photoresist material, and in the first mask process, the photoresist material is divided into four portions exposed under four exposure degrees that is gradually reduced from a full exposure degree to a non-exposure degree, the four portions that the exposure degrees are gradually decreased are respectively removed after developing in order to form the first photoresist pattern, the second photoresist pattern and the third photoresist pattern.

### Claim 5 (depends on 3)

The manufacturing method for amorphous silicon TFT substrate according to claim 3, wherein in the step S9, the coated photoresist material is a positive photoresist material, and in the third mask process, the photoresist material is divided into three portions exposed under three exposure degrees that are from a full exposure degree to a non-exposure degree. The three portions exposed under the three exposure degrees are respectively removed after being developed in order to formed a fourth photoresist pattern and a fifth photoresist pattern.

### Claim 6 (depends on 1)

The manufacturing method for amorphous silicon TFT substrate according to claim 1, wherein a material of each of the first transparent conductive layer and the second transparent conductive layer is indium tin oxide (ITO).

### Claim 7 (depends on 1)

The manufacturing method for amorphous silicon TFT substrate according to claim 1, wherein in the step S1, the amorphous silicon layer, the N-type doped amorphous silicon layer, and the first transparent conductive layer are formed by a chemical vapor deposition (CVD), the source drain metal layer is formed by a sputter method.

### Claim 8 (depends on 1)

The manufacturing method for amorphous silicon TFT substrate according to claim 1, wherein in the step S8, the passivation layer is formed by a chemical vapor deposition.

### Claim 9 (depends on 1)

The manufacturing method for amorphous silicon TFT substrate according to claim 1, wherein in the step S9, the second transparent conductive layer is deposited by a chemical vapor deposition, and the gate metal layer is formed by a sputter method.

### Claim 10 (depends on 1)

The manufacturing method for amorphous silicon TFT substrate according to claim 1, wherein in the step S1, the N-type doped amorphous silicon layer 30 is formed by adding phosphine during the deposition process.