# US 2019/0355835 A1 · Structure and formation method of semiconductor device structure with nanowires

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- Number: US 2019/0355835 A1
- Document ID: US20190355835A1
- Status: Published application
- Kind: A1
- Application number: 16/528,768
- Filed: 2019-08-01
- Published: 2019-11-21
- Earliest claimed: 2017-08-31
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Chao-Ching CHENG; Wei-Sheng YUN; Shao-Ming YU; Tsung-Lin LEE; Chih-Chieh YEH
- Web page: https://patentgrep.com/patent/US20190355835A1

## CPC

- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/122: {oriented at angles to substrates, e.g. perpendicular to substrates}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/01: Manufacture or treatment
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/251: {Source or drain electrodes for field-effect devices}
- H10D 64/512: {Disposition of the gate electrodes, e.g. buried gates}
- H10D 64/514: {characterised by the insulating layers}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 84/853: {comprising FinFETs}
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10D 88/01: {Manufacture or treatment}
- H10W 10/0121: {in regions recessed from the surface, e.g. in trenches or grooves}
- H10W 10/13: formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a plurality of nanowires over an input-output region, and a protective layer surrounding the nanowires. The protective layer is made of silicon, silicon germanium, silicon oxide, silicon nitride, silicon sulfide, or a combination thereof. The semiconductor device structure also includes a high-k dielectric layer surrounding the protective layer, and a gate electrode surrounding the high-k dielectric layer. The semiconductor device structure further includes a source/drain portion adjacent to the gate electrode, and an interlayer dielectric layer over the source/drain portion.

## Claims

### Claim 1

A semiconductor device structure, comprising:
a substrate having a plurality of nanowires over an input-output region;
a protective layer surrounding the nanowires, wherein the protective layer is made of silicon, silicon germanium, silicon oxide, silicon nitride, silicon sulfide, or a combination thereof;
a high-k dielectric layer surrounding the protective layer;
a gate electrode surrounding the high-k dielectric layer;
a source/drain portion adjacent to the gate electrode; and
an interlayer dielectric layer over the source/drain portion.

### Claim 2 (depends on 1)

The semiconductor device structure as claimed in claim 1, further comprising:
an etch stop layer between the source/drain portion and the interlayer dielectric layer; and
a protective element over the interlayer dielectric layer, wherein a sidewall of the interlayer dielectric layer and a sidewall of the protective element are covered by the etch stop layer.

### Claim 3 (depends on 1)

The semiconductor device structure as claimed in claim 1, further comprising:
a dielectric layer surrounding the protective layer; and
an additional layer surrounding the dielectric layer, wherein the additional layer comprises a silicon element, a nitrogen element, and/or a sulfur element, and wherein the dielectric layer is separated from the high-k dielectric layer by the additional layer.

### Claim 4 (depends on 1)

The semiconductor device structure as claimed in claim 1, wherein the substrate has a fin portion in the input-output region, the nanowires are disposed over the fin portion, and a portion of the protective layer extends below a top surface of the fin portion.

### Claim 5 (depends on 1)

The semiconductor device structure as claimed in claim 1, further comprising:
a second protective layer over a topmost nanowire of the nanowires; and
a spacer element over the second protective layer, wherein an upper portion of the protective layer is separated from the source/drain portion by the second protective layer and the spacer element, a lower portion of the protective layer is separated from the source/drain portion by a plurality of semiconductor layers, and the semiconductor layers and the nanowires are made of different materials.

### Claim 6

A semiconductor device structure, comprising:
a substrate having a first fin portion in an input-output region and a second fin portion in a core region;
a first nanowire over the first fin portion in the input-output region;
a second nanowire over the second fin portion in the core region;
a dielectric layer surrounding the first nanowire;
a first gate structure surrounding the dielectric layer and the first nanowire;
a first source/drain portion adjacent to the first gate structure;
a second gate structure surrounding the second nanowire; and
a second source/drain portion adjacent to the second gate structure.

### Claim 7 (depends on 6)

The semiconductor device structure as claimed in claim 6, further comprising:
a first protective layer between the dielectric layer and the first nanowire; and
a second protective layer between the second gate structure and the second nanowire.

### Claim 8 (depends on 6)

The semiconductor device structure as claimed in claim 6, further comprising:
a first additional layer between the dielectric layer and the first gate structure in the input-output region.

### Claim 9 (depends on 7)

The semiconductor device structure as claimed in claim 7, further comprising:
a second additional layer between the second protective layer and the second gate structure in the core region.

### Claim 10 (depends on 9)

The semiconductor device structure as claimed in claim 9, wherein the second additional layer is in direct contact with the second protective layer.

### Claim 11 (depends on 6)

The semiconductor device structure as claimed in claim 6, further comprising:
a protective element over the first source/drain portion, wherein a top surface of the protective element is coplanar with a top surface of the first gate structure.

### Claim 12 (depends on 6)

The semiconductor device structure as claimed in claim 6, wherein the first gate structure further comprises a high-k dielectric layer surrounding the dielectric layer, and a gate electrode surrounding the high-k dielectric layer.

### Claim 13 (depends on 6)

The semiconductor device structure as claimed in claim 6, further comprising:
a spacer element over the first nanowire and between the first source/drain structure and the first gate structure, wherein the dielectric layer extends over a sidewall of the spacer element.

### Claim 14

A semiconductor device structure, comprising:
a substrate having a fin portion in an input-output region;
a nanowire over the fin portion in the input-output region;
a gate structure surrounding the nanowire and having opposite sides;
two spacer elements adjacent to the opposite sides of the gate structure;
a dielectric layer between the spacer elements and the gate structure; and
two source/drain portions adjacent to the two spacer elements respectively.

### Claim 15 (depends on 14)

The semiconductor device structure as claimed in claim 14, further comprising:
an etch stop layer over each of the source/drain portions;
an interlayer dielectric layer over the etch stop layer; and
a protective element over the interlayer dielectric layer, wherein a material of the protective element is different from a material of the interlayer dielectric layer.

### Claim 16 (depends on 15)

The semiconductor device structure as claimed in claim 15, wherein sidewalls of the protective element are separated from the gate structure by the etch stop layer and the spacer elements.

### Claim 17 (depends on 14)

The semiconductor device structure as claimed in claim 14, wherein the nanowire is made of silicon, silicon germanium, germanium tin, silicon germanium tin, gallium arsenide, indium gallium arsenide, indium arsenide, or a combination thereof.

### Claim 18 (depends on 14)

The semiconductor device structure as claimed in claim 14, wherein the dielectric layer is made of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

### Claim 19 (depends on 14)

The semiconductor device structure as claimed in claim 14, further comprising:
an additional layer between the dielectric layer and the gate structure.

### Claim 20 (depends on 19)

The semiconductor device structure as claimed in claim 19, wherein the additional layer comprises a silicon element, a nitrogen element, and/or a sulfur element.