# US 2019/0355833 A1 · Vertical field effect transistors with self aligned source/drain junctions

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- Number: US 2019/0355833 A1
- Document ID: US20190355833A1
- Status: Published application
- Kind: A1
- Application number: 15/980,111
- Filed: 2018-05-15
- Published: 2019-11-21
- Earliest claimed: 2018-05-15
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Xin Miao; Chen Zhang; Kangguo Cheng; Wenyu Xu
- Web page: https://patentgrep.com/patent/US20190355833A1

## CPC

- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 62/292: {Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512)}
- H10D 64/01352: {with sacrificial oxide}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/018: {Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates}
- H10P 32/1408: {from or through or into an external applied layer, e.g. photoresist or nitride layers}
- H10P 32/171: {being group IV material}
- H10P 95/90: Thermal treatments, e.g. annealing or sintering
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 62/832: being Group IV materials comprising two or more elements, e.g. SiGe
- H10D 62/8325: {Silicon carbide}
- H10D 62/852: being Group III-V materials comprising three or more elements, e.g. AlGaN or InAsSbP
- H10D 62/8603: {Binary Group II-VI materials wherein cadmium is the Group II element, e.g. CdTe}
- H10D 62/862: being Group II-VI materials comprising three or more elements, e.g. CdZnTe
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method of controlling an effective gate length in a vertical field effect transistor is provided. The method includes forming a vertical fin on a substrate, and forming a bottom spacer layer on the substrate adjacent to the vertical fin. The method further includes forming a dummy gate block adjacent to the vertical fin on the bottom spacer layer. The method further includes forming a top spacer adjacent to the vertical fin on the dummy gate block, and removing the dummy gate block to expose a portion of the vertical fin between the top spacer and bottom spacer layer. The method further includes forming an absorption layer on the exposed portion of the vertical fin. The method further includes heat treating the absorption layer and vertical fin to form a dopant modified absorption layer, and removing the dopant modified absorption layer.

## Claims

### Claim 1

A method of controlling an effective gate length in a vertical field effect transistor, comprising:
forming a vertical fin on a substrate, wherein the vertical fin includes a dopant species;
forming a bottom spacer layer on the substrate adjacent to the vertical fin;
forming a dummy gate block adjacent to the vertical fin on the bottom spacer layer;
forming a top spacer adjacent to the vertical fin on the dummy gate block;
removing the dummy gate block to expose a portion of the vertical fin between the top spacer and bottom spacer layer;
forming an absorption layer on the exposed portion of the vertical fin;
heat treating the absorption layer and vertical fin to form a dopant modified absorption layer, wherein the heat treatment causes at least a portion of the dopant species to diffuse/segregate from the vertical fin to the absorption layer to form the dopant modified absorption layer; and
removing the dopant modified absorption layer.

### Claim 2 (depends on 1)

The method of claim 1, wherein the absorption layer is formed by a rapid thermal oxidation or atomic layer deposition (ALD).

### Claim 3 (depends on 1)

The method of claim 1, wherein the absorption layer is an in-situ steam generation (ISSG) oxide layer formed through wet oxidation of the exposed portion of the vertical fin.

### Claim 4

(canceled)

### Claim 5 (depends on 1)

The method of claim 1, wherein the vertical fin includes the dopant species in a concentration in a range of about 1×1018 atoms/cm−3 to about 1×1020 atoms/cm−3.

### Claim 6 (depends on 5)

The method of claim 5, further comprising forming a gate dielectric layer on the portion of the vertical fin exposed by removing the dopant modified absorption layer.

### Claim 7 (depends on 6)

The method of claim 6, further comprising forming a conductive gate layer on the gate dielectric layer.

### Claim 8 (depends on 7)

The method of claim 7, further comprising forming a top source/drain on the vertical fin.

### Claim 9 (depends on 8)

The method of claim 8, wherein the dummy gate block has a thickness in a range of about 10 nm to about 50 nm.

### Claim 10

A method of controlling an effective gate length in a vertical field effect transistor, comprising:
forming a vertical fin layer on a substrate, wherein the vertical fin layer includes a dopant species;
forming a plurality of vertical fins from the vertical fin layer, wherein the vertical fins include the dopant species;
forming a bottom source/drain layer on the substrate adjacent to each of the plurality of vertical fins;
forming a bottom spacer layer on the bottom source/drain layer adjacent to each of the plurality of vertical fins;
forming a dummy gate block adjacent to each of the plurality of vertical fins on the bottom spacer layer;
forming a top spacer adjacent to each of the plurality of vertical fins on the dummy gate block;
removing the dummy gate blocks to expose a portion of each of the plurality of vertical fins between the top spacer and bottom spacer layer;
forming an absorption layer on the exposed portion of each of the plurality of vertical fins; and
heat treating the absorption layer and plurality of vertical fins to diffuse/segregate at least a portion of the dopant species from the vertical fins to the absorption layer to form a dopant modified absorption layer.

### Claim 11 (depends on 10)

The method of claim 10, further comprising removing the dopant modified absorption layer, and forming a gate dielectric layer on the portion of the vertical fin exposed by removing the dopant modified absorption layer.

### Claim 12 (depends on 11)

The method of claim 11, wherein the plurality of vertical fins are made of a semiconductor material selected from the group consisting of group IV semiconductors, group IV-IV semiconductors, group III-V semiconductors, and group II-VI semiconductors.

### Claim 13 (depends on 12)

The method of claim 12, wherein the vertical fins can have a width in a range of about 4 nm to about 20 nm.

### Claim 14 (depends on 12)

The method of claim 12, wherein the heat treatment is conducted at a temperature in a range of about 700° C. to about 1200° C.

### Claim 15

A vertical field effect transistor with self-aligned source/drain junctions, comprising:
a vertical fin on a substrate, wherein the vertical fin has a lower portion and an upper portion with a first dopant concentration; and
a reduced dopant region between the upper portion of the vertical fin and the lower portion of the vertical fin with a second dopant concentration less than the first dopant concentration.

### Claim 16 (depends on 15)

The vertical field effect transistor of claim 15, further comprising a gate dielectric layer on the reduced dopant region, and a conductive gate layer on the gate dielectric layer, and wherein the first dopant concentration is in a range of about 1×1018 cm−3 to about 1×1020 cm−3, and the second dopant concentration is in a range of about 1×1016 cm−3 to about 1×1018 cm−3.

### Claim 17 (depends on 16)

The vertical field effect transistor of claim 16, wherein the reduced dopant region, gate dielectric layer, and conductive gate layer forms a vertical gate structure with an effective gate length in a range of about 10 nm to about 50 nm.

### Claim 18 (depends on 17)

The vertical field effect transistor of claim 17, further comprising a bottom source/drain layer adjacent to at least a portion of the lower fin region, and a top source/drain on the vertical fin.

### Claim 19 (depends on 18)

The vertical field effect transistor of claim 18, further comprising a top spacer and a top source/drain on the vertical fin.

### Claim 20 (depends on 19)

The vertical field effect transistor of claim 19, wherein the vertical fin is made of a semiconductor material selected from the group consisting of silicon (Si), silicon carbide (SiC), silicon-germanium (SiGe), germanium (Ge)), gallium-arsenide (GaAs), indium-gallium-arsenide (InGaAs), indium-phosphide (InP), indium-antimonide (InSb), cadmium-telluride (CdTe), zinc-telluride (ZnTe), zinc sulfide (ZnS), and zinc selenide (ZnSe).