# US 2019/0355829 A1 · Interface-less contacts to source/drain regions and gate electrode over active portion of device

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- Number: US 2019/0355829 A1
- Document ID: US20190355829A1
- Status: Published application
- Kind: A1
- Application number: 15/982,507
- Filed: 2018-05-17
- Published: 2019-11-21
- Earliest claimed: 2018-05-17
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Junli Wang; Veeraraghavan S. Basker; Huiming Bu
- Web page: https://patentgrep.com/patent/US20190355829A1

## CPC

- H10D 30/0212: {using self-aligned silicidation}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10P 14/6902: {composed of carbon, e.g. alpha-C, diamond or hydrogen doped carbon}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method of providing contact surfaces that includes forming a first mask having an opening to a perimeter of a gate electrode, the first mask having a first protecting portion centrally positioned over the gate electrode within the perimeter, and a second protecting portion of the mask is positioned over metal semiconductor alloy surfaces of source and drain contact surfaces; and recessing exposed portions of metal semiconductor alloy and the gate electrode with an etch. In a following step, the method continues with filling the openings provided by recessing the gate perimeter of the gate electrode, recessing the metal semiconductor alloy adjacent to the gate structure, and the recessed gate electrode adjacent to the metal semiconductor alloy surface of the source and drain contact surfaces with a protecting dielectric material.

## Claims

### Claim 1

A method of providing contact surfaces for gate electrodes and source and drain regions of a semiconductor device comprising:
forming a hard mask having an opening to a perimeter of a gate electrode of a gate structure, the hard mask having a first protecting portion centrally positioned over the gate electrode within the perimeter, and a second protecting portion of the mask is positioned over metal semiconductor alloy surfaces of source and drain contact surfaces;
recessing exposed portions of metal semiconductor alloy adjacent to the gate structure, the gate perimeter of the gate electrode, and a portion of the gate electrode adjacent to the metal semiconductor alloy surface as the source and drain contact surfaces with an etch, wherein the portion of the gate electrode protected by the first protecting portion of the hard mask provides the gate electrode contact surface; and
filling the openings provided by recessing the gate perimeter of the gate electrode, recessing the metal semiconductor alloy adjacent to the gate structure, and the recessed gate electrode adjacent to the metal semiconductor alloy surface of the source and drain contact surfaces with a protecting dielectric material.

### Claim 2 (depends on 1)

The method of claim 1, wherein the protecting dielectric material has an upper surface that is coplanar with an upper surface of the gate electrode contact surface, and the source and drain contact surfaces.

### Claim 3 (depends on 2)

The method of claim 2, wherein the protecting dielectric material comprises silicon boron carbon nitride (SiBCN).

### Claim 4 (depends on 1)

The method of claim 1, wherein forming the hard mask comprises:
forming a photoresist mask including openings for the hard mask;
depositing a dielectric material for the hard mask in the openings for the hard mask that are present in the photoresist mask;
planarizing the dielectric material; and
removing the photoresist mask.

### Claim 5 (depends on 1)

The method of claim 1, wherein said recessing comprises an anisotropic etch process.

### Claim 6 (depends on 1)

The method of claim 1, further comprising planarizing the protective dielectric material.

### Claim 7

A method for forming a contact to the gate electrodes and source and drain regions of a semiconductor device comprising:
forming a hard mask having an opening to a perimeter of a gate electrode, the hard mask having a first protecting portion centrally positioned over the gate electrode within the perimeter, and a second protecting portion of the hard mask is positioned over metal semiconductor alloy surfaces of source and drain contact surfaces;
recessing exposed portions of metal semiconductor alloy and the gate electrode;
filling the openings provided by recessing the gate perimeter of the gate electrode, recessing the metal semiconductor alloy adjacent to the gate structure, and the recessed gate electrode adjacent to the metal semiconductor alloy surface of the source and drain contact surfaces with a protecting dielectric material; and
forming contacts to exposed portions of the upper surface of the gate electrode contact surface and the source and drain contact surfaces.

### Claim 8 (depends on 7)

The method of claim 7, wherein the protecting dielectric material has an upper surface that is coplanar with an upper surface of the gate electrode contact surface, and the source and drain contact surfaces.

### Claim 9 (depends on 8)

The method of claim 8, wherein the protecting dielectric material comprises silicon boron carbon nitride (SiBCN).

### Claim 10 (depends on 7)

The method of claim 7, wherein forming the hard mask comprises:
forming a photoresist mask including openings for the hard mask;
depositing a dielectric material for the hard mask in the openings for the hard mask that are present in the photoresist mask;
planarizing the dielectric material; and
removing the photoresist mask.

### Claim 11 (depends on 7)

The method of claim 7, wherein said recessing comprises an anisotropic etch process.

### Claim 12 (depends on 7)

The method of claim 7, further comprising planarizing the protective dielectric material.

### Claim 13 (depends on 7)

The method of claim 7, wherein forming said contacts comprises:
depositing an interlevel dielectric layer;
forming via openings to the gate electrode and the metal semiconductor alloy surfaces of source and drain contact surfaces; and
filling the via openings with electrically conductive material.

### Claim 14 (depends on 13)

The method of claim 13, wherein the protective dielectric material obstructs the contacts to the gate electrode from shorting to the contacts to the metal semiconductor alloy surfaces of the source and drain contact surfaces.

### Claim 15 (depends on 13)

The method of claim 13, wherein the contacts are present over an active region of the semiconductor device.

### Claim 16

A semiconductor device comprising:
a gate structure including a gate electrode and source and drain regions on opposing sides of the gate structure, the gate electrode having an upper surface including a pedestal, wherein a protective dielectric is present around the perimeter of the pedestal, wherein a base surface of the protective dielectric is present on a non-pedestal surface of the gate electrode, and an upper surface of the protective dielectric is coplanar with an upper surface of the pedestal; and
contacts present to the upper surface of the pedestal and the source and drain regions.

### Claim 17 (depends on 16)

The semiconductor device of claim 16, wherein the semiconductor device is a FinFET.

### Claim 18 (depends on 16)

The semiconductor device of claim 16, wherein the semiconductor device is a planar semiconductor device.

### Claim 19 (depends on 16)

The semiconductor device of claim 16, wherein the contact to the pedestal of the gate electrode is present in an active region of the semiconductor device.

### Claim 20 (depends on 16)

The semiconductor device of claim 16, wherein protective dielectric material obstructs the contacts to the gate electrode from shorting to the contacts to the metal semiconductor alloy surfaces of the source and drain contact surfaces.