# US 2019/0355828 A1 · Semiconductor apparatus

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- Number: US 2019/0355828 A1
- Document ID: US20190355828A1
- Status: Published application
- Kind: A1
- Application number: 16/316,855
- Filed: 2017-07-13
- Published: 2019-11-21
- Earliest claimed: 2016-07-15
- Assignees: Rohm Co., Ltd.
- Applicants: Rohm Co., Ltd.
- Inventors: Kenji YAMAMOTO; Masatoshi AKETA; Hirokazu ASAHARA; Takashi NAKAMURA; Takuji HOSOI; Heiji WATANABE; Takayoshi SHIMURA; Shuji AZUMO; Yusaku KASHIWAGI
- Web page: https://patentgrep.com/patent/US20190355828A1

## CPC

- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 30/66: Vertical DMOS [VDMOS] FETs
- H10D 64/011: {of electrodes ohmically coupled to a semiconductor}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D 64/685: {being perpendicular to the channel plane}
- H10P 14/40: of conductive or resistive materials
- H10D 62/80: characterised by the materials
- H10D 62/8303: {Diamond}
- H10D 62/8325: {Silicon carbide}
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device has an MIS structure that includes a semiconductor layer, a gate insulating film on the semiconductor layer, and a gate electrode on the gate insulating film. The gate insulating film has a layered structure that includes a base SiO2 layer and a high-k layer on the base SiO2 layer and containing Hf. The gate electrode has a portion made of a metal material having a work function of higher than 4.6 eV, the portion being in contact with at least the high-k layer.

## Claims

### Claim at position 1

1-18. (canceled)

### Claim 19

A semiconductor device comprising an MIS structure including:
a semiconductor layer having a front surface and a rear surface;
a gate insulating film formed on the front surface side in the semiconductor layer; and
a gate electrode formed on the gate insulating film,
wherein the gate insulating film has a layered structure that includes a base SiO2 layer and a high-k layer on the base SiO2 layer and containing Hf, and
the gate electrode has a portion made of a metal material having a work function of higher than 4.6 eV, the portion being in contact with at least the high-k layer.

### Claim 20

A semiconductor device comprising an MIS structure including:
a semiconductor layer having a front surface and a rear surface;
a gate insulating film formed on the front surface side in the semiconductor layer; and
a gate electrode formed on the gate insulating film,
wherein the gate insulating film has a layered structure that includes a base SiO2 layer, a high-k layer on the base SiO2 layer and containing Hf, and an upper insulating layer between the high-k layer and the gate electrode, and
the upper insulating layer is made of a material having a difference of lower than 4 eV between a lowest energy Ec in the conduction band and a vacuum energy level.

### Claim 21

A semiconductor device comprising an MIS structure including:
a semiconductor layer having a front surface and a rear surface;
a gate insulating film formed on the front surface side in the semiconductor layer; and
a gate electrode formed on the gate insulating film,
wherein the gate insulating film has a layered structure that includes a base SiO2 layer and a high-k layer on the base SiO2 layer and containing Hf, and
the gate electrode has a portion made of Mo, Cu, Au, Ni, Pt or TiN, the portion being in contact with at least the high-k layer.

### Claim 22

A semiconductor device comprising an MIS structure including:
a semiconductor layer having a front surface and a rear surface;
a gate insulating film formed on the front surface side in the semiconductor layer; and
a gate electrode formed on the gate insulating film,
wherein a variation rate of a post-test threshold voltage after a negative stress voltage of a predetermined magnitude is applied to the gate electrode for 30 minutes or longer to an initial threshold voltage of the gate electrode is within 20%.

### Claim 23 (depends on 20)

The semiconductor device according to claim 20, wherein the upper insulating layer is made of SiO2 and has a thickness of 5 nm or more.

### Claim 24 (depends on 19)

The semiconductor device according to claim 19, wherein the high-k layer includes an HfAlON layer.

### Claim 25 (depends on 24)

The semiconductor device according to claim 24, wherein the HfAlON layer has an Hf composition (Hf/(Hf+Al)) of 30% to 70%.

### Claim 26 (depends on 24)

The semiconductor device according to claim 24, wherein the HfAlON layer has an N amount of 10 at % or less.

### Claim 27 (depends on 24)

The semiconductor device according to claim 24, wherein the HfAlON layer has a thickness of 10 nm to 200 nm.

### Claim 28 (depends on 24)

The semiconductor device according to claim 24, wherein the HfAlON layer is amorphous or microcrystalline.

### Claim 29 (depends on 19)

The semiconductor device according to claim 19, wherein the base SiO2 layer has a thickness of 5 nm or more.

### Claim 30 (depends on 19)

The semiconductor device according to claim 19, wherein the semiconductor layer is made of SiC, GaN, Ga2O3, or diamond.

### Claim 31 (depends on 19)

The semiconductor device according to claim 19, wherein the MIS structure includes a trench gate type structure.

### Claim 32 (depends on 19)

The semiconductor device according to claim 19, wherein the MIS structure includes a planar gate structure.

### Claim 33 (depends on 31)

The semiconductor device according to claim 31, wherein the gate insulating film is formed so as to cover a side surface and a bottom surface of a gate trench formed by being dug from the front surface of the semiconductor layer and a portion of the front surface of the semiconductor layer.

### Claim 34 (depends on 33)

The semiconductor device according to claim 33, wherein
the gate electrode is embedded in the gate trench, and
the semiconductor device includes:
a source region of a first conductivity type formed on the front surface side in the semiconductor layer so as to contact the side surface of the gate trench, a body region of a second conductivity type formed closer to the rear surface side in the semiconductor layer than the source region, a drain region of a first conductivity type formed closer to the rear surface side in the semiconductor layer than the body region,
an interlayer insulating film formed so as to cover an upper portion of the gate electrode,
a source electrode electrically connected to the source region, and
a drain electrode electrically connected to the drain region.

### Claim 35 (depends on 34)

The semiconductor device according to claim 34, comprising a source trench formed at a position away from the gate trench so as to penetrate the source region and the body region by being dug from the front surface of the semiconductor layer so that the source electrode is embedded inside the source trench.

### Claim 36 (depends on 35)

The semiconductor device according to claim 35, wherein a second conductivity type region is formed around the source trench so as to be continuous to the body region.