# US 2019/0355809 A1 · Semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0355809 A1 - Document ID: US20190355809A1 - Status: Published application - Kind: A1 - Application number: 16/529,564 - Filed: 2019-08-01 - Published: 2019-11-21 - Earliest claimed: 2018-04-16 - Assignees: Panasonic Intellectual Property Management Co., Ltd. - Applicants: Panasonic Intellectual Property Management Co., Ltd. - Inventors: Teruhisa IKUTA; Hiroshi SAKURAI; Satoru KANAI - Web page: https://patentgrep.com/patent/US20190355809A1 ## CPC - H10D 62/106: {having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions} - H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]} - H10D 64/112: {comprising multiple field plate segments} - H10D 64/251: {Source or drain electrodes for field-effect devices} - H10D 30/67: Thin-film transistors [TFT] {(Stacked nanowire, nanosheet or nanoribbon FETs H10D30/501)} - H10D 30/6717: {the source and the drain regions being asymmetrical} - H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions} - H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs} - H10D 62/371: {Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract In a semiconductor device including first and second conductive plates (FFPs) formed by being stacked in layer, the first conductive plate and the second conductive plate include linear regions elongated to face each other along a longitudinal direction in which a length with which source region and drain region elongated in parallel face each other is longest, and are elongated in a short-side direction orthogonal to the longitudinal direction. Here, high voltage wiring of either one of source wiring and drain wiring is elongated in the short-side direction to intersect the linear regions of the first conductive plate and the second conductive plate, and low voltage wiring of the other one of source wiring and drain wiring is elongated in the short-side direction to intersect at least one linear region of the first conductive plate or the second conductive plate. ## Claims ### Claim 1 A semiconductor device, comprising: a semiconductor layer located on a principal surface of a supporting substrate; a body region located in an upper portion of the semiconductor layer, the body region having a first conductivity type; a drain region located in an upper portion of the semiconductor layer, the drain region having a second conductivity type, the drain region being apart from the body region; a source region located in an upper portion of the body region, the source region having the second conductivity type; a drift region located between the drain region and the body region in the semiconductor layer, the drift region having the second conductivity type; a first insulator region located in an upper portion of the semiconductor layer, the first insulator region being located between the body region and the drain region, the first insulator region overlapping the drift region; a gate insulation film located on the semiconductor layer, the gate insulation film being located from a part on the body region to an end portion of the first insulator region; a gate electrode located on at least part of the gate insulation film and at least part of the first insulator region; at least one first conductive plate located on the first insulator region, the at least one first conductive plate being located between the gate electrode and the drain region, the at least one first conductive plate being in an electrically floating state; a second insulator region located on the first insulator region, the gate electrode, and the at least one first conductive plate; at least one second conductive plate located on the second insulator region where at least the gate electrode and the at least one first conductive plate are not located, the at least one second conductive plate being in an electrically floating state; a third insulator region located on the second insulator region, above the gate electrode and on the at least one second conductive plate; source wiring located above the third insulator region, the source wiring electrically connected to the source region; and drain wiring located above the third insulator region, the drain wiring electrically connected to the drain region, wherein in plan view, the source region and the drain region are elongated along a longitudinal direction that is a direction in which facing lengths are longest, and are disposed side by side in a short-side direction that is a direction orthogonal to the longitudinal direction, in plan view, the at least one first conductive plate and the at least one second conductive plate each have a linear region elongated along the longitudinal direction to face each other, and a curved region connecting terminal end portions of the linear regions in the longitudinal direction in a folded line or circular arc shape, in plan view, high voltage wiring of either one of the source wiring and the drain wiring is elongated in the short-side direction to intersect the linear regions of the at least one first conductive plate and the at least one second conductive plate, and in plan view, low voltage wiring of the other one of the source wiring and the drain wiring is elongated in the short-side direction to intersect at least one of (i) the linear region of the at least one first conductive plate and (ii) the linear region of the one second conductive plate. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein a buried insulation film is located between the supporting substrate and the semiconductor layer. ### Claim 3 (depends on 1) The semiconductor device according to claim 1, wherein in plan view, a high voltage side region of either one of the source region and the drain region is completely surrounded by a low voltage side region of the other one of the source region and the drain region, and in plan view, the high voltage side region is completely surrounded by the at least one first conductive plate and the at least one second conductive plate. ### Claim 4 (depends on 1) The semiconductor device according to claim 1, wherein in plan view, the low voltage wiring intersects the linear region of each of the at least one first conductive plate and the linear region of each of the at least one second conductive plate. ### Claim 5 (depends on 1) The semiconductor device according to claim 1, wherein in plan view, a width in the longitudinal direction where the linear region of the at least one first conductive plate and the linear region of the at least one second conductive plate overlap the low voltage wiring is reducing or increasing toward a high voltage side region of either one of the drain region and the source region. ### Claim 6 (depends on 1) The semiconductor device according to claim 1, wherein in plan view, the source wiring and the drain wiring that intersect the linear region of the at least one first conductive plate, and the linear region of the at least one second conductive plate are elongated side by side in the longitudinal direction, and a space in the longitudinal direction between the source wiring and the drain wiring is narrower than widths in the longitudinal direction of the source wiring and the drain wiring. ### Claim 7 (depends on 6) The semiconductor device according to claim 6, wherein in plan view, a plurality of the source wirings and a plurality of the drain wirings that intersect the linear region of the at least one first conductive plate and the linear region of the at least one second conductive plate are alternately disposed in the longitudinal direction. ### Claim 8 (depends on 1) The semiconductor device according to claim 1, wherein in plan view, a ratio of a total dimension in the longitudinal direction of a part where the linear region of the at least one first conductive plate and the linear region of the at least one second conductive plate overlap the high voltage wiring, and a total dimension in the longitudinal direction of a part where the linear region of the at least one first conductive plate and the linear region of the at least one second conductive plate overlap the low voltage wiring is in a range of ⅓ to 3 inclusive. ### Claim 9 A semiconductor device, comprising: a semiconductor layer located on a principal surface of a supporting substrate; a body region located in an upper portion of the semiconductor layer, the body region having a first conductivity type; a drain region located in an upper portion of the semiconductor layer, the drain region having a second conductivity type, the drain region being apart from the body region; a source region located in an upper portion of the body region, the source region having the second conductivity type; a drift region located between the drain region and the body region in the semiconductor layer, the drift region having the second conductivity type; a first insulator region located in an upper portion of the semiconductor layer, the first insulator region being located between the body region and the drain region, the first insulator region overlapping the drift region; a gate insulation film located on the semiconductor layer, the gate insulation film being located from a part on the body region to an end portion of the first insulator region; a gate electrode located on at least part of the gate insulation film and at least part of the first insulator region; at least one conductive plate located on the first insulator region, the at least one conductive plate being located between the gate electrode and the drain region, the at least one conductive plate being in an electrically floating state; a second insulator region located on the first insulator region, the gate electrode, and the at least one conductive plate; source wiring located above the second insulator region, the source wiring electrically connected to the source region; and drain wiring located above the second insulator region, the drain wiring electrically connected to the drain region, wherein in plan view, the source region and the drain region are elongated along a longitudinal direction that is a direction in which facing lengths are longest, and are disposed side by side in a short-side direction that is a direction orthogonal to the longitudinal direction, in plan view, the at least one conductive plate each have a linear region elongated along the longitudinal direction to face each other, and a curved region connecting terminal end portions of the linear regions in the longitudinal direction in a folded line or circular arc shape, in plan view, high voltage wiring of either one of the source wiring and the drain wiring is elongated in the short-side direction to intersect the linear regions of the at least one conductive plate, in plan view, low voltage wiring of the other one of the source wiring and the drain wiring is elongated in the short-side direction to intersect the linear region of the at least one conductive plate, and an interval in a short-side direction between the at least one conductive plate and the gate electrode adjacent to the at least one conductive plate or an interval in a short-side direction between adjacent conductive plates among the at least one conductive plate is shorter than a thickness of the second insulator region. ### Claim 10 (depends on 9) The semiconductor device according to claim 9, wherein a buried insulation film is located between the supporting substrate and the semiconductor layer. ### Claim 11 (depends on 9) The semiconductor device according to claim 9, wherein in plan view, a high voltage side region of either one of the source region and the drain region is completely surrounded by a low voltage side region of the other one of the source region and the drain region, and in plan view, the high voltage side region is completely surrounded by the at least one conductive plate.