# US 2019/0355799 A1 · Thin film transistor substrate, method of manufacturing the same, and display device including the same

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- Number: US 2019/0355799 A1
- Document ID: US20190355799A1
- Status: Published application
- Kind: A1
- Application number: 16/412,059
- Filed: 2019-05-14
- Published: 2019-11-21
- Earliest claimed: 2018-05-18
- Assignees: Samsung Display Co., Ltd.
- Applicants: Samsung Display Co., Ltd.
- Inventors: WOO HO JEONG; SEOKJE SEONG; SEMYUNG KWON; YOON HO KIM; BYUNGJU LEE
- Web page: https://patentgrep.com/patent/US20190355799A1

## CPC

- H10K 59/1213: {the pixel elements being TFTs}
- H10K 59/1216: {the pixel elements being capacitors}
- H10K 59/124: Insulating layers formed between TFT elements and OLED elements
- H10K 59/131: Interconnections, e.g. wiring lines or terminals
- H10K 77/111: {Flexible substrates}
- H10D 30/0314: {of lateral top-gate TFTs comprising only a single gate}
- H10D 30/0321: {comprising silicon, e.g. amorphous silicon or polysilicon}
- H10D 30/6731: {Top-gate only TFTs}
- H10D 30/6745: {Polycrystalline or microcrystalline silicon}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 86/021: {of multiple TFTs}
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/471: {having different architectures, e.g. having both top-gate and bottom-gate TFTs}
- H10D 86/481: {integrated with passive devices, e.g. auxiliary capacitors}
- H10D 86/60: wherein the TFTs are in active matrices
- H10D 99/00: Subject matter not provided for in other groups of this subclass
- H10K 59/1201: {Manufacture or treatment}
- H10K 2102/311: {Flexible OLED}
- Y02E 10/549: Organic PV cells
- Y02P 70/50: Manufacturing or production processes characterised by the final manufactured product
- H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- Y02E: REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02P: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS

## Abstract

A TFT substrate includes a first active pattern, a first gate insulation, and a first gate. A second gate is on a second gate insulation covering the first gate. A source connection electrode contacts a source region of the first active pattern. A drain connection electrode contacts its drain region. A second active pattern is on a first insulation covering the second gate. A third gate insulation covers the second active pattern. A third gate is disposed on the third gate insulation. A second insulation interlayer covers the third gate. A first source, a first drain, a second source, and a second drain are disposed on the second insulation interlayer. The first source and the first drain contact the source connection electrode and the drain connection electrode. The second source and the second drain contact a source region and a drain region of the second active pattern.

## Claims

### Claim 1

A thin film transistor (TFT) substrate, comprising:
a base substrate;
a first active pattern disposed on the base substrate;
a first gate insulation layer at least partially covering the first active pattern;
a first gate electrode disposed on the first gate insulation layer, the first gate electrode forming a first thin film transistor with the first active pattern;
a second gate insulation layer at least partially covering the first gate electrode;
a second gate electrode disposed on the second gate insulation layer, the second gate electrode at least partially overlapping the first gate electrode;
a source connection electrode contacting a source region of the first active pattern;
a drain connection electrode contacting a drain region of the first active pattern;
a first insulation interlayer at least partially covering the second gate electrode;
a second active pattern disposed on the first insulation layer;
a third gate insulation layer at least partially covering the second active pattern;
a third gate electrode disposed on the third gate insulation layer, the third gate electrode forming a second thin film transistor with the second active pattern;
a second insulation interlayer at least partially covering the third gate electrode; and
a first source electrode, a first drain electrode, a second source electrode, and a second drain electrode each disposed on the second insulation interlayer, the first source electrode and the first drain electrode contacting the source connection electrode and the drain connection electrode, respectively, and the second source electrode and the second drain electrode contacting a source region and a drain region of the second active pattern, respectively.

### Claim 2 (depends on 1)

The TFT substrate of claim 1, wherein the source connection electrode, the drain connection electrode, and the second gate electrode are all disposed within a common layer.

### Claim 3 (depends on 1)

The TFT substrate of claim 1, wherein the source connection electrode, the drain connection electrode, and the first gate electrode are all disposed within a common layer.

### Claim 4 (depends on 1)

The TFT substrate of claim 1, wherein:
the source connection electrode is connected to the source region of the first active pattern through a first contact hole, and
the drain connection electrode is connected to the drain region of the first active pattern through a second contact hole.

### Claim 5 (depends on 4)

The TFT substrate of claim 4, wherein:
the first source electrode is connected to the source connection electrode through a third contact hole, and
the first drain electrode is connected to the drain connection electrode through a fourth contact hole.

### Claim 6 (depends on 5)

The TFT substrate of claim 5, wherein a smallest width of the first contact hole and a smallest width of the second contact hole are greater than a largest width of the third contact hole and a largest width of the fourth contact hole, respectively.

### Claim 7 (depends on 1)

The TFT substrate of claim 1, wherein:
one of the first active pattern and the second active pattern includes a polycrystalline silicon semiconductor, and
the other of the first active pattern and the second active pattern includes an oxide semiconductor.

### Claim 8

A method of manufacturing a thin film transistor substrate, comprising:
forming a first active pattern on a base substrate;
forming a first gate insulation layer at least partially covering the first active pattern;
forming a first gate electrode on the first gate insulation layer, the first gate electrode forming a first thin film transistor with the first active pattern;
forming a second gate insulation layer at least partially covering the first gate electrode;
forming a second gate electrode on the second gate insulation layer, the second gate electrode at least partially overlapping the first gate electrode;
forming a source connection electrode in contact with a source region of the first active pattern;
forming a drain connection electrode in contact with a drain region of the first active pattern;
forming a first insulation interlayer at least partially covering the second gate electrode;
forming a second active pattern on the first insulation layer;
forming a third gate insulation layer at least partially covering the second active pattern;
forming a third gate electrode on the third gate insulation layer, the third gate electrode forming a second thin film transistor with the second active pattern;
forming a second insulation interlayer at least partially covering the third gate electrode; and
forming each of a first source electrode, a first drain electrode, a second source electrode, and a second drain electrode on the second insulation interlayer, the first source electrode and the first drain electrode contacting the source connection electrode and the drain connection electrode, respectively, and the second source electrode and the second drain electrode contacting a source region and a drain region of the second active pattern, respectively.

### Claim 9 (depends on 8)

The method of claim 8, wherein the source connection electrode, the drain connection electrode, and the second gate electrode are formed within a common layer at substantially the same time.

### Claim 10 (depends on 9)

The method of claim 9, wherein forming the second gate electrode, and forming the source connection electrode and the drain connection electrode comprise:
forming a first contact hole and a second contact hole passing through the first gate insulation layer and the second gate insulation layer, the first contact hole and the second contact hole exposing a portion of the source region and a portion of the drain region of the first active pattern, respectively;
forming a conductive layer connected to the source region and the drain region of the first active pattern through the first contact hole and the second contact hole, respectively, on the second gate insulation layer; and
etching the conductive layer to form the second gate electrode, the source connection electrode, and the drain connection electrode.

### Claim 11 (depends on 8)

The method of claim 8, wherein the source connection electrode, the drain connection electrode, and the first gate electrode are formed within a common layer at substantially the same time.

### Claim 12 (depends on 11)

The method of claim 11, wherein forming the first gate electrode, and forming the source connection electrode and the drain connection electrode comprise:
forming a first contact hole and a second contact hole passing through the first gate insulation layer, the first contact hole and the second contact hole exposing a portion of the source region and a portion of the drain region of the first active pattern, respectively;
forming a conductive layer connected to the source region and the drain region of the first active pattern through the first contact hole and the second contact hole, respectively, on the first gate insulation layer; and
etching the conductive layer to form the first gate electrode, the source connection electrode, and the drain connection electrode.

### Claim 13 (depends on 8)

The method of claim 8, wherein forming the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode comprises:
forming a first contact hole and a second contact hole exposing a portion of the source connection electrode and a portion of the drain connection electrode, respectively;
forming a third contact hole and a fourth contact hole exposing a portion of the source region and a portion of the drain region of the second active pattern, respectively;
forming a conductive layer connected to the source connection electrode, the drain connection electrode, and the source region and the drain region of the second active pattern through the first contact hole, the second contact hole, the third contact hole, and the fourth contact hole, respectively, on the second insulation interlayer; and
etching the conductive layer to form the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode.

### Claim 14 (depends on 13)

The method of claim 13, wherein forming the third contact hole and forming the fourth contact hole are each performed after forming both the first contact hole and the second contact hole.

### Claim 15 (depends on 13)

The method of claim 13, wherein the third contact hole, the fourth contact hole, the first contact hole, and the second contact hole are all formed at substantially the same time.

### Claim 16

A display device, comprising:
a base substrate;
a first active pattern disposed on the base substrate;
a first gate insulation layer at least partially covering the first active pattern;
a first gate electrode disposed on the first gate insulation layer, the first gate electrode forming a first thin film transistor with the first active pattern;
a second gate insulation layer at least partially covering the first gate electrode;
a second gate electrode disposed on the second gate insulation layer, the second gate electrode at least partially overlapping the first gate electrode;
a source connection electrode contacting a source region of the first active pattern;
a drain connection electrode contacting a drain region of the first active pattern;
a first insulation interlayer at least partially covering the second gate electrode;
a second active pattern disposed on the first insulation layer;
a third gate insulation layer at least partially covering the second active pattern;
a third gate electrode disposed on the third gate insulation layer, the third gate electrode forming a second thin film transistor with the second active pattern;
a second insulation interlayer at least partially covering the third gate electrode;
a first source-drain pattern disposed on the second insulation interlayer, the first source-drain pattern including a first source electrode and a first drain electrode contacting the source connection electrode and the drain connection electrode, respectively, and a second source electrode and a second drain electrode contacting a source region and a drain region of the second active pattern, respectively;
a first planarization layer at least partially covering the first source-drain pattern; and
a light emitting structure disposed on the first planarization layer, the light emitting structure being electrically connected to the first thin film transistor.

### Claim 17 (depends on 16)

The display device of claim 16, wherein the source connection electrode, the drain connection electrode, and the second gate electrode are all disposed within a common layer.

### Claim 18 (depends on 16)

The display device of claim 16, wherein the source connection electrode, the drain connection electrode, and the first gate electrode are all disposed within a common layer.

### Claim 19 (depends on 16)

The display device of claim 16, wherein:
one of the first active pattern and the second active pattern includes a polycrystalline silicon semiconductor, and
the other of the first active pattern and the second active pattern includes an oxide semiconductor.

### Claim 20 (depends on 16)

The display device of claim 16, wherein the light emitting structure includes:
a first electrode disposed on the first planarization layer, the first electrode being electrically connected to the first drain electrode;
an organic light emitting layer disposed on the first electrode; and
a second electrode disposed on the organic light emitting layer.

### Claim 21 (depends on 20)

The display device of claim 20, wherein the base substrate includes:
a first area;
a second area spaced apart from the first area; and
a bending area between the first area and the second area,
wherein the first thin film transistor is disposed on the first area,
wherein the second thin film transistor is disposed on the first area,
wherein a capacitor is disposed on the first area, the capacitor including the first gate electrode and the second gate electrode, and
wherein the light emitting structure is disposed on the first area.

### Claim 22 (depends on 21)

The display device of claim 21, further comprising an organic layer disposed on the base substrate within the bending area,
wherein the first source-drain pattern further includes a first wiring disposed on the organic layer.

### Claim 23 (depends on 22)

The display device of claim 22, further comprising:
a second planarization layer disposed between the first planarization layer and the first electrode; and
a second source-drain pattern disposed between the first planarization layer and the second planarization layer, the second source-drain pattern including a pixel connection electrode electrically connecting the first drain electrode to the first electrode and a second wiring within the bending area, the second wiring being electrically connected to the first wiring.