# US 2019/0355756 A1 · Dynamic logic built with stacked transistors sharing a common gate

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- Number: US 2019/0355756 A1
- Document ID: US20190355756A1
- Status: Published application
- Kind: A1
- Application number: 15/774,556
- Filed: 2015-12-26
- Published: 2019-11-21
- Earliest claimed: 2015-12-26
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Donald W. NELSON; Rishabh MEHANDRU
- Web page: https://patentgrep.com/patent/US20190355756A1

## CPC

- H10D 86/215: {comprising FinFETs}
- H03K 19/0963: {using transistors of complementary type (H03K19/0966 takes precedence)}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 84/0172: {Manufacturing their gate conductors}
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/853: {comprising FinFETs}
- H10D 86/011: {comprising FinFETs}
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10D 88/01: {Manufacture or treatment}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A dynamic logic circuit including a first transistor within a first device stratum of a substrate; and a second transistor within a second device stratum of the substrate that is different from the first device stratum, wherein the first transistor and the second transistor share a common gate electrode. A method including disposing a second semiconductor body of a second transistor on a first semiconductor body of a first transistor in a first device stratum on a substrate, the second semiconductor body defining a second device stratum; and forming a common gate electrode on each of the semiconductor body and the second semiconductor body.

## Claims

### Claim 1

A dynamic logic circuit comprising:
a first transistor comprising a first semiconductor body within a first device stratum of a substrate; and
a second transistor comprising a second semiconductor body within a second device stratum of the substrate that is different from the first device stratum, wherein the first transistor and the second transistor share a common gate electrode.

### Claim 2 (depends on 1)

The dynamic logic circuit of claim 1, wherein the first transistor comprises a precharge transistor and the second transistor comprises an evaluate transistor.

### Claim 3 (depends on 2)

The dynamic logic circuit of claim 2, wherein the first transistor comprises a P-type MOSFET.

### Claim 4 (depends on 1)

The dynamic logic circuit of claim 1, wherein the first semiconductor body and the second transistor body each comprise a fin.

### Claim 5 (depends on 1)

The dynamic logic circuit of claim 1, wherein the gate electrode wraps around the first semiconductor body and the second transistor body.

### Claim 6 (depends on 1)

The dynamic logic circuit of claim 1, further comprising an inter-strata interconnect coupled to a drain of the first transistor and a drain of the second transistor.

### Claim 7 (depends on 6)

The dynamic logic circuit of claim 6, wherein the inter-strata interconnect is coupled to an output line, the circuit further comprising an inverter cell coupled to the output line.

### Claim 8 (depends on 7)

The dynamic logic circuit of claim 7, wherein the inverter cell comprises a P-type MOSFET and an N-type MOSFET that share a common gate electrode.

### Claim 9

A dynamic logic circuit comprising:
a P-type MOSFET comprising a clock input;
an N-type MOSFET logic circuit comprising one or more N-type MOSFETs comprising one or more logic inputs and an N-type MOSFET comprising the clock input; and
an inverter cell coupled to the N-type logic circuit,
wherein the P-type MOSFET is in a different device stratum of a substrate than the N-type MOSFET comprising the clock input and the P-type MOSFET and the N-type MOSFET comprising the clock input share a common gate electrode.

### Claim 10 (depends on 9)

The dynamic logic circuit of claim 9, wherein a source of the P-type MOSFET is coupled to a power source.

### Claim 11 (depends on 9)

The dynamic logic circuit of claim 9, further comprising an inter-stratum interconnect coupled to the drain of the P-type MOSFET and the drain of the N-type MOSFET comprising the clock input.

### Claim 12 (depends on 11)

The dynamic logic circuit of claim 11, wherein the inter-stratum interconnect is coupled to an output line and the inverter cell is coupled to the output line.

### Claim 13 (depends on 9)

The dynamic logic circuit of claim 9, wherein the inverter cell comprises a P-type MOSFET and an N-type MOSFET that share a common gate electrode.

### Claim 14 (depends on 13)

The dynamic logic circuit of claim 13, wherein the P-type MOSFET and the N-type MOSFET of the inverter cell are in different device strata on the substrate.

### Claim 15

A method comprising:
disposing a second semiconductor body of a second transistor on a first semiconductor body of a first transistor in a first device stratum on a substrate, the second semiconductor body defining a second device stratum; and
forming a common gate electrode on each of the semiconductor body and the second semiconductor body.

### Claim 16 (depends on 15)

The method of claim 15, wherein one of the first transistor and the second transistor comprises a P-type MOSFET and the other of the first transistor and the second transistor comprises an N-type MOSFET.

### Claim 17 (depends on 16)

The method of claim 16, further comprising forming an inter-strata interconnect coupled to a drain of the first transistor and a drain of the second transistor.

### Claim 18 (depends on 17)

The method of claim 17, wherein the inter-strata interconnect is coupled to an output line, the method further comprising forming an inverter cell coupled to the output line.

### Claim 19 (depends on 18)

The method of claim 18, wherein the inverter cell comprises a P-type MOSFET and an N-type MOSFET that share a common gate electrode.

### Claim 20 (depends on 19)

The method of claim 19, wherein one of the P-type MOSFET and the N-type MOSFET of the inverter cell is formed in the first device stratum and the other of the P-type MOSFET and the N-type MOSFET of the inverter cell is formed in the second device stratum.