# US 2019/0355754 A1 · Display panel

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- Number: US 2019/0355754 A1
- Document ID: US20190355754A1
- Status: Published application
- Kind: A1
- Application number: 16/527,002
- Filed: 2019-07-30
- Published: 2019-11-21
- Earliest claimed: 2017-05-12
- Assignees: Au Optronics Corporation
- Applicants: Au Optronics Corporation
- Inventors: Cheng-Kuang Wang; Chun-Da Tu
- Web page: https://patentgrep.com/patent/US20190355754A1

## CPC

- H10D 86/60: wherein the TFTs are in active matrices
- G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters}
- G11C 19/28: using semiconductor elements (G11C19/14, G11C19/36 take precedence)
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/481: {integrated with passive devices, e.g. auxiliary capacitors}
- G09G 3/2092: {Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto (suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165)}
- G09G 2300/0408: Integration of the drivers onto the display substrate
- G09G 2300/0809: Several active elements per pixel in active matrix panels
- G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A display panel including a display region and a non-display region, a plurality of gate lines, a plurality of data lines, a pixel array and a gate on array circuit. The non-display region is located at one side of the display region. The plurality of gate lines and the plurality of data lines are disposed in the display region. The pixel array is located in the display region, wherein the pixel array is composed of a plurality of pixel units that are repeatedly arranged. The pixel units consist of three gate lines, two data lines and six sub-pixels, and each sub-pixel is electrically connected to one of the gate lines and one of the data lines located in the pixel array respectively. The gate on array circuit is disposed in the pixel array.

## Claims

### Claim 1

A display panel, comprising:
a pixel array, having a plurality of pixel units, and the pixel array comprising:
a plurality of gate lines and a plurality of data lines; and
a plurality of sub-pixels, electrically connected to one of the plurality of gate lines and one of the plurality of data lines respectively, wherein each of the plurality of pixel units comprises two gate lines, three data lines and six sub-pixels; and
a gate driver circuit, disposed in the pixel array.

### Claim 2 (depends on 1)

The display panel according to claim 1, wherein a width of each of the plurality of sub-pixels in an extending direction of the plurality of gate lines is larger than a width of each of the plurality of sub-pixels in an extending direction of the plurality of data lines.

### Claim 3 (depends on 1)

The display panel according to claim 1, wherein the gate driver circuit comprises a plurality of driving units, each of the plurality of driving units comprises a plurality of active elements, a plurality of signal lines and a plurality of capacitors, wherein one of the plurality of signal lines is substantially parallel with the plurality of data lines or the plurality of gate lines.

### Claim 4 (depends on 3)

The display panel according to claim 3, wherein the plurality of signal lines comprise a power signal line, a first clock signal line, a second clock signal line, a pre-stage input line, a post-stage input line and an output line, wherein the pre-stage input line, the post-stage input line and the output line are respectively electrically connected to three gate lines.

### Claim 5 (depends on 4)

The display panel according to claim 4, wherein each of the plurality of driving units comprises:
a first active element, having a control end, a first end and a second end, wherein the control end is electrically connected to the post-stage input line, and the second end is electrically connected to the power signal line;
a second active element, having a control end, a first end and a second end, wherein the control end is electrically connected to the first end of the first active element, and the second end is electrically connected to the power signal line;
a third active element, having a control end, a first end and a second end, wherein the control end is electrically connected to the first end of the second active element, the first end is electrically connected to the first end of the first active element, and the second end is electrically connected to the power signal line;
a fourth active element, having a control end, a first end and a second end, wherein the control end and the first end are electrically connected to the pre-stage input line, the second end is electrically connected to the first end of the first active element;
a fifth active element, having a control end, a first end and a second end, wherein the control end is electrically connected to the second clock signal line, the first end is electrically connected to the output line, and the second end is electrically connected to the power signal line;
a sixth active electrically, having a control end, a first end and a second end, wherein the control end is electrically connected to the first end of the second active element, the first end is electrically connected to the output line, and the second end is electrically connected to the power signal line;
a seventh active element, having a control end, a first end and a second end, wherein the control end is electrically connected to the first end of the first active element, the first end is electrically connected to the first clock signal, and the second end is electrically connected to the output line.

### Claim 6 (depends on 5)

The display panel according to claim 5, wherein each of the plurality of driving units further comprises:
a first capacitor, electrically connected to the output line and the first end of the first active element respectively; and
a second capacitor, electrically connected to the first clock signal line and the first end of the second active element respectively.

### Claim 7 (depends on 5)

The display panel according to claim 5, wherein in one of the driving units, the first active element, the fourth active element, the fifth active element and the seventh active element are disposed on the same horizontal line along an extending direction of the plurality of gate lines, and the second active element, the third active element and the sixth active element are disposed on another horizontal line along the extending direction of the plurality of gate lines.

### Claim 8 (depends on 1)

The display panel according to claim 1, wherein one of the plurality of pixel units comprises a first data line, a second data line, a third data line, a first gate line, a second gate line and first to sixth sub-pixels, and the first sub-pixel is electrically connected to the first gate line and the first data line respectively, the second sub-pixel is electrically connected to the first gate line and the second data line respectively, the third sub-pixel is electrically connected to the second gate line and the first data line respectively, the fourth sub-pixel is electrically connected to the first gate line and the third data line respectively, the fifth sub-pixel is electrically connected to the second gate line and the second data line respectively, the sixth sub-pixel is electrically connected to the second gate line and the third data line respectively, wherein the second sub-pixel and the fifth sub-pixel are disposed between the first gate line and the second gate line, and the first sub-pixel, the second sub-pixel and the third sub-pixel are disposed between the first data line and the second data line.

### Claim 9 (depends on 8)

The display panel according to claim 8, wherein the one of the plurality of pixel units further comprises a third gate line, a fourth gate line and seventh to twelfth sub-pixels, and the seventh sub-pixel is electrically connected to the third gate line and the second data line respectively, the eighth sub-pixel is electrically connected to the third gate line and the third data line respectively, the ninth sub-pixel is electrically connected to the fourth gate line and the second data line respectively, the tenth sub-pixel is electrically connected to the third gate line and a fourth data line respectively, the eleventh sub-pixel is electrically connected to the fourth gate line and the third data line respectively, the twelfth sub-pixel is electrically connected to the fourth gate line and the fourth data line respectively, wherein the eighth sub-pixel and the eleventh sub-pixel are disposed between the third gate line and the fourth gate line, and the seventh sub-pixel, the eighth sub-pixel and the ninth sub-pixel are disposed between the first data line and the second data line.

### Claim 10 (depends on 1)

The display panel according to claim 1, wherein the gate driver circuit comprises a plurality of active elements and a plurality of signal lines, the plurality of active elements are disposed between two adjacent pixel units, the plurality of signal lines are disposed between the two adjacent pixel units or two adjacent sub-pixels.

### Claim 11 (depends on 1)

The display panel according to claim 1, wherein the gate driver circuit comprises a first driving unit and a second driving unit, the first driving unit and the second driving unit respectively have a plurality of active elements, and arrangement of the plurality of active elements of the first driving unit is identical with arrangement of the plurality of active elements of the second driving unit.

### Claim 12 (depends on 1)

The display panel according to claim 1, wherein the gate driver circuit comprises a first driving unit and a second driving unit, the first driving unit and the second driving unit respectively have a plurality of active elements, and arrangement of the plurality of active elements of the first driving unit is mirror symmetrical to arrangement of the plurality of active elements of the second driving unit.