# US 2019/0355753 A1 · Display panel and method of manufacturing the same

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- Number: US 2019/0355753 A1
- Document ID: US20190355753A1
- Status: Published application
- Kind: A1
- Application number: 16/461,677
- Filed: 2017-05-05
- Published: 2019-11-21
- Earliest claimed: 2016-12-30
- Assignees: Hkc Corporation Limited; Chongqing Hkc Optoelectronics Technology Co., Ltd.
- Applicants: HKC Corporation Limited; Chongqing HKC Optoelectronics Technology Co., Ltd.
- Inventors: Yu-Jen CHEN
- Web page: https://patentgrep.com/patent/US20190355753A1

## CPC

- G02F 1/136286: {Wiring, e.g. gate line, drain line}
- H10D 86/60: wherein the TFTs are in active matrices
- G02F 1/134363: {for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]}
- H10D 30/6729: {characterised by the electrodes}
- H10D 30/6739: {Conductor-insulator-semiconductor electrodes}
- H10D 86/021: {of multiple TFTs}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- G02F 1/136: Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit (G02F1/135 takes precedence)
- G02F 1/13629: {Multilayer wirings}
- G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A display panel includes a substrate and a first layer of wires. The first layer of wires are disposed on the substrate. A lower portion of the first layer of wires includes a first high attachment metal layer, an upper portion of the first layer of wires includes a second high attachment metal layer, and a middle of the first layer of wires includes an intermediate electroconductive layer. The first layer of wires are connected to a column scan driver of the display panel.

## Claims

### Claim 1

A display panel, comprising:
a substrate; and
a first layer of wires disposed on the substrate, wherein a lower portion of the first layer of wires comprises a first high attachment metal layer, an upper portion of the first layer of wires comprises a second high attachment metal layer, a middle of the first layer of wires comprises an intermediate electroconductive layer, and the first layer of wires are connected to a column scan driver of the display panel;
wherein a thickness of the intermediate electroconductive layer is greater than a thickness of the first high attachment metal layer and a thickness of the second high attachment metal layer; a width of a bottom portion of the intermediate electroconductive layer is greater than a width of a top portion of the intermediate electroconductive layer, a width of the first high attachment metal layer is the same as the width of the bottom portion of the intermediate electroconductive layer, a width of the second high attachment metal layer is the same as the width of the top portion of the intermediate electroconductive layer; the intermediate electroconductive layer is made of copper, aluminum, silver, gold, chromium, molybdenum, or any or their alloys; and the first high attachment metal layer and the second high attachment metal layer are made of molybdenum or a molybdenum alloy;
wherein an insulating layer is disposed on a wire segment of a gate, a semiconductor layer corresponding to the wire segment of the gate is disposed on the insulating layer, a source and a drain of a thin film transistor separated from each other are disposed on two ends of the semiconductor layer, a trench is disposed between the source and the drain, and a bottom portion of the trench is the semiconductor layer;
wherein the first layer of wires are integrally covered with the first high attachment metal layer and the second high attachment metal layer, the insulating layer is disposed on the first layer of wires, the first layer of wires comprise the wire segment of the gate disposed on the thin film transistor, the semiconductor layer corresponding to the wire segment of the gate is disposed on the insulating layer, the source and the drain of the thin film transistor separated from each other are disposed on two ends of the semiconductor layer, the trench is disposed between the source and the drain, and the bottom portion of the trench is the semiconductor layer.

### Claim 2

A display panel, comprising:
a substrate; and
a first layer of wires disposed on the substrate, wherein a lower portion of the first layer of wires comprises a first high attachment metal layer, an upper portion of the first layer of wires comprises a second high attachment metal layer, a middle of the first layer of wires comprises an intermediate electroconductive layer, and the first layer of wires are connected to a column scan driver of the display panel.

### Claim 3 (depends on 2)

The display panel according to claim 2, wherein a thickness of the intermediate electroconductive layer is greater than a thickness of the first high attachment metal layer and a thickness of the second high attachment metal layer.

### Claim 4 (depends on 2)

The display panel according to claim 2, wherein a width of a bottom portion of the intermediate electroconductive layer is greater than a width of a top portion of the intermediate electroconductive layer, a width of the first high attachment metal layer is the same as the width of the bottom portion of the intermediate electroconductive layer, and a width of the second high attachment metal layer is the same as the width of the top portion of the intermediate electroconductive layer.

### Claim 5 (depends on 2)

The display panel according to claim 2, wherein the intermediate electroconductive layer is made of copper, aluminum, silver, gold, chromium, molybdenum, or any of their alloys.

### Claim 6 (depends on 2)

The display panel according to claim 2, wherein the first high attachment metal layer and the second high attachment metal layer are made of molybdenum or a molybdenum alloy.

### Claim 7 (depends on 2)

The display panel according to claim 2, wherein the first layer of wires comprise a wire segment of a gate disposed on a thin film transistor; and the first layer of wires are disposed with the second high attachment metal layer only on the wire segment of the gate.

### Claim 8 (depends on 7)

The display panel according to claim 7, wherein an insulating layer is disposed on the wire segment of the gate, a semiconductor layer corresponding to the wire segment of the gate is disposed on the insulating layer, a source and a drain of a thin film transistor separated from each other are disposed on two ends of the semiconductor layer, a trench is disposed between the source and the drain, and a bottom portion of the trench is the semiconductor layer.

### Claim 9 (depends on 2)

The display panel according to claim 2, wherein the first layer of wires are integrally covered with the first high attachment metal layer and the second high attachment metal layer, an insulating layer is disposed on the first layer of wires, the first layer of wires comprise a wire segment of a gate disposed on a thin film transistor, a semiconductor layer corresponding to the wire segment of the gate is disposed on the insulating layer, a source and a drain of the thin film transistor separated from each other are disposed on two ends of the semiconductor layer, a trench is disposed between the source and the drain, and a bottom portion of the trench is the semiconductor layer.

### Claim 10

A method of manufacturing a display panel, comprising steps of:
disposing a first high attachment metal layer on a substrate;
disposing an intermediate electroconductive layer on the first high attachment metal layer;
disposing a second high attachment metal layer on the intermediate electroconductive layer; and
etching the first high attachment metal layer, the intermediate electroconductive layer and the second high attachment metal layer to form a first layer of wires.

### Claim 11 (depends on 1)

The method according to claim 1, wherein the intermediate electroconductive layer is etched to have a top portion and a bottom portion wider than the top portion, the first high attachment metal layer is etched to have a width the same as a width of the bottom portion of the intermediate electroconductive layer, and the second high attachment metal layer is etched to have a width the same as a width of the top portion of the intermediate electroconductive layer.

### Claim 12 (depends on 11)

The method according to claim 11, wherein the intermediate electroconductive layer is made of copper, aluminum, silver, gold, chromium, molybdenum, or any of their alloys.

### Claim 13 (depends on 11)

The method according to claim 11, wherein the first high attachment metal layer and the second high attachment metal layer are made of molybdenum or a molybdenum alloy.

### Claim 14 (depends on 11)

The method according to claim 11, wherein the first layer of wires comprise a wire segment of a gate disposed on a thin film transistor; and the first layer of wires are disposed with the second high attachment metal layer only on the wire segment of the gate.

### Claim 15 (depends on 14)

The method according to claim 14, wherein an insulating layer is disposed on the wire segment of the gate, a semiconductor layer corresponding to the wire segment of the gate is disposed on the insulating layer, a source and a drain of the thin film transistor separated from each other are disposed on two ends of the semiconductor layer, a trench is disposed between the source and the drain, and a bottom portion of the trench is the semiconductor layer.

### Claim 16 (depends on 11)

The method according to claim 11, wherein the first layer of wires are integrally covered with the first high attachment metal layer and the second high attachment metal layer, an insulating layer is disposed on the first layer of wires, the first layer of wires comprise a wire segment of a gate disposed on a thin film transistor, a semiconductor layer corresponding to the wire segment of the gate is disposed on the insulating layer, a source and a drain of the thin film transistor separated from each other are disposed on two ends of the semiconductor layer, a trench is disposed between the source and the drain, and a bottom portion of the trench is the semiconductor layer.