# US 2019/0355752 A1 · Thin film transistor array substrate and manufacturing method thereof

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- Number: US 2019/0355752 A1
- Document ID: US20190355752A1
- Status: Published application
- Kind: A1
- Application number: 16/438,385
- Filed: 2019-06-11
- Published: 2019-11-21
- Earliest claimed: 2010-01-14
- Assignees: Samsung Display Co., Ltd.
- Applicants: Samsung Display Co., Ltd.
- Inventors: Young-Wook LEE; Woo-Geun LEE; Ki-Won KIM; Hyun-Jung LEE; Ji-Soo OH
- Web page: https://patentgrep.com/patent/US20190355752A1

## CPC

- H10D 86/60: wherein the TFTs are in active matrices
- H10D 30/6756: {Amorphous oxide semiconductors}
- H10D 86/0212: {comprising manufacture, treatment or coating of substrates}
- H10D 86/0221: {comprising manufacture, treatment or patterning of TFT semiconductor bodies}
- H10D 86/0231: {using masks, e.g. half-tone masks}
- H10D 86/411: {characterised by materials, geometry or structure of the substrates}
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/481: {integrated with passive devices, e.g. auxiliary capacitors}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A substrate including a gate line and a gate electrode disposed on a substrate, an oxide semiconductor layer pattern overlapping the gate electrode, a gate insulating layer disposed between the gate electrode and the oxide semiconductor layer pattern, a data line intersecting the gate line, a source electrode electrically connected to the oxide semiconductor layer pattern, a drain electrode electrically connected to the oxide semiconductor layer, the drain electrode spaced apart from the source electrode, and an insulating pattern including a first portion, which is disposed between the gate line and the data line and at least partially overlaps with both of the gate line and the data line.

## Claims

### Claim 1

A substrate, comprising:
a gate line and a gate electrode disposed on a substrate;
an oxide semiconductor layer pattern overlapping the gate electrode;
a gate insulating layer disposed between the gate electrode and the oxide semiconductor layer pattern;
a data line intersecting the gate line;
a source electrode electrically connected to the oxide semiconductor layer pattern;
a drain electrode electrically connected to the oxide semiconductor layer, the drain electrode spaced apart from the source electrode; and
an insulating pattern comprising a first portion, which is disposed between the gate line and the data line and at least partially overlaps with both of the gate line and the data line.

### Claim 2 (depends on 1)

The substrate of claim 1, wherein the insulating pattern further comprises a second portion, which is disposed between the source electrode, the drain electrode, and the oxide semiconductor layer pattern, and at least partially overlaps with the gate electrode.

### Claim 3 (depends on 1)

The substrate of claim 1, further comprising a storage line disposed on the same layer as the gate line and the gate electrode,
wherein the insulating pattern further comprises a third portion, which is disposed between the storage line and the data line, and at least partially overlaps with both the data line and the storage line.

### Claim 4 (depends on 1)

The substrate of claim 1, wherein the insulating pattern comprises at least one of silicon oxide and silicon nitride.

### Claim 5 (depends on 1)

The substrate of claim 1, further comprising a low-k dielectric material pattern disposed on or under the insulating pattern to form a stacked structure together with the insulating pattern.

### Claim 6 (depends on 5)

The substrate of claim 5, wherein the low-k dielectric material pattern comprises at least one material selected from the group consisting of SiBN, SiCN, BCN, BN, and CN.

### Claim 7 (depends on 5)

The substrate of claim 5, wherein a thickness of the low-k dielectric material pattern is greater than a thickness of the insulating pattern.

### Claim 8 (depends on 1)

The substrate of claim 1, further comprising a transparent organic layer pattern disposed on the insulating pattern to form a stacked structure together with the insulating pattern.

### Claim 9 (depends on 8)

The substrate of claim 8, wherein the transparent organic layer pattern is used as an etch mask for patterning the insulating pattern.

### Claim 10 (depends on 1)

The substrate of claim 1, wherein the insulating pattern is disposed on the gate insulating layer.

### Claim 11 (depends on 1)

The substrate of claim 1, wherein the source electrode and the drain electrode directly contact the oxide semiconductor layer pattern.